GitHub - gowrivlsi/VERILOG_CODES_PROJECTS: Collection of RTL and Verilog projects including FIFO designs, FSM systems, parameterized RAM, and PCIe SERDES implementation with testbenches, waveforms, and schematics.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
FIFO_Design		FIFO_Design
FSM-Based Bus Booking System		FSM-Based Bus Booking System
PARAM_RAM		PARAM_RAM
PCIE[SERDES]		PCIE[SERDES]

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Collection of RTL and Verilog projects including FIFO designs, FSM systems, parameterized RAM, and PCIe SERDES implementation with testbenches, waveforms, and schematics.

fsm ram serdes simulation fifo testbench pcie