Standard Cell Design Project – SKY130

📌 Project Overview

This repository documents my ongoing work on CMOS standard cell design using the SKY130 (130nm) PDK.
The objective of this project is to understand and implement the complete standard cell design flow from schematic to layout-level verification.

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✅ Work Completed

• Transistor-level design of:
  • CMOS Inverter (INV)
  • 2-Input NAND Gate
  • 2-Input NOR Gate
• SPICE simulation using NGSPICE
• Physical layout design using Magic
• Design Rule Check (DRC) verification
• Parasitic extraction from layout
• Switch-level functional verification using IRSIM

This work demonstrates understanding of:

• Pull-up and Pull-down network design
• CMOS logic implementation
• Layout design rules (130nm)
• Basic ASIC standard cell development flow

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🔄 Current Focus

• Layout optimization and area improvement
• Propagation delay analysis
• Power estimation fundamentals
• Preparing for integration into larger digital design flows

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🗓 Estimated Completion

May 2026

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🎯 Long-Term Goal

The long-term objective of this project is to transition from CMOS standard cell design to GaN-based circuit drivers, focusing on high-speed and high-power device applications.

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📈 Project Status

🟢 Ongoing – Continuous updates and improvements will be pushed to this repository.