ARC-V RHX-100 upstream patch series

gcc/config.gcc

@@ -560,7 +560,7 @@ riscv*)
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-string.o"
 	extra_objs="${extra_objs} riscv-v.o riscv-vsetvl.o riscv-vector-costs.o riscv-avlprop.o riscv-vect-permconst.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o sifive-vector-builtins-bases.o andes-vector-builtins-bases.o"
-	extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o riscv-bclr-lowest-set-bit.o riscv-opt-popretz.o"
+	extra_objs="${extra_objs} thead.o riscv-target-attr.o riscv-zicfilp.o riscv-bclr-lowest-set-bit.o riscv-opt-popretz.o arcv.o"
 	d_target_objs="riscv-d.o"
 	extra_headers="riscv_vector.h riscv_crypto.h riscv_bitmanip.h riscv_th_vector.h sifive_vector.h andes_vector.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"

gcc/config/riscv/arcv-rhx100.md

@@ -0,0 +1,106 @@
+;; DFA scheduling description of the Synopsys RHX-100 cpu
+;; for GNU C compiler
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "arcv_rhx100")
+
+(define_cpu_unit "arcv_rhx100_ALU_A_fuse0_early"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_A_fuse1_early"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_B_fuse0_early"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_B_fuse1_early"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_MPY32"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DIV"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DMP_fuse0"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DMP_fuse1"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_fdivsqrt"	"arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueA_fuse0" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueA_fuse1" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueB_fuse0" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueB_fuse1" "arcv_rhx100")
+
+;; Instruction reservation for arithmetic instructions (pipe A, pipe B).
+(define_insn_reservation "arcv_rhx100_alu_early_arith" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "unknown,move,const,arith,shift,slt,multi,auipc,nop,logical,\
+		bitmanip,min,max,minu,maxu,clz,ctz,atomic,\
+		condmove,mvpair,zicond,cpop,clmul"))
+  "((arcv_rhx100_issueA_fuse0 + arcv_rhx100_ALU_A_fuse0_early) | (arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse1_early)) | ((arcv_rhx100_issueB_fuse0 + arcv_rhx100_ALU_B_fuse0_early) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse1_early))")
+
+(define_insn_reservation "arcv_rhx100_imul_fused" 4
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "imul_fused"))
+  "(arcv_rhx100_issueA_fuse0 + arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse0_early + arcv_rhx100_ALU_A_fuse1_early + arcv_rhx100_MPY32), nothing*3")
+
+(define_insn_reservation "arcv_rhx100_alu_fused" 1
+   (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "alu_fused"))
+  "(arcv_rhx100_issueA_fuse0 + arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse0_early + arcv_rhx100_ALU_A_fuse1_early) | (arcv_rhx100_issueB_fuse0 + arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse0_early + arcv_rhx100_ALU_B_fuse1_early)")
+
+(define_insn_reservation "arcv_rhx100_jmp_insn" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "arcv_rhx100_issueA_fuse0 | arcv_rhx100_issueA_fuse1")
+
+(define_insn_reservation "arcv_rhx100_div_insn" 12
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "idiv"))
+  "arcv_rhx100_issueA_fuse0 + arcv_rhx100_DIV, nothing*11")
+
+(define_insn_reservation "arcv_rhx100_mpy32_insn" 4
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "imul"))
+  "arcv_rhx100_issueA_fuse0 + arcv_rhx100_MPY32, nothing*3")
+
+(define_insn_reservation "arcv_rhx100_load_insn" 3
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "load,fpload"))
+  "(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
+
+(define_insn_reservation "arcv_rhx100_store_insn" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "store,fpstore"))
+  "(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
+
+;; (soft) floating points
+(define_insn_reservation "arcv_rhx100_xfer" 3
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
+  "(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early), nothing*2")
+
+(define_insn_reservation "arcv_rhx100_fmul" 5
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "fadd,fmul,fmadd"))
+  "(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)")
+
+(define_insn_reservation "arcv_rhx100_fdiv" 20
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "fdiv,fsqrt"))
+  "arcv_rhx100_fdivsqrt*20")
+
+;; Bypasses
+(define_bypass 1 "arcv_rhx100_alu_early_arith" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
+
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_alu_early_arith")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_mpy*_insn")
+(define_bypass 2 "arcv_rhx100_load_insn" "arcv_rhx100_load_insn")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_div_insn")
+
+(define_bypass 3 "arcv_rhx100_mpy32_insn" "arcv_rhx100_mpy*_insn")
+(define_bypass 3 "arcv_rhx100_mpy32_insn" "arcv_rhx100_div_insn")

gcc/config/riscv/arcv-rmx100.md

@@ -0,0 +1,104 @@
+;; DFA scheduling description of the Synopsys RMX-100 cpu
+;; for GNU C compiler
+;; Copyright (C) 2025 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "arcv_rmx100")
+
+(define_cpu_unit "arcv_rmx100_ALU"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_FPU"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_MPY"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_DIV"    "arcv_rmx100")
+(define_cpu_unit "arcv_rmx100_DMP"    "arcv_rmx100")
+
+;; Instruction reservation for arithmetic instructions.
+(define_insn_reservation "arcv_rmx100_alu_arith" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "unknown, const, arith, shift, slt, multi, auipc, nop,
+			logical, move, atomic, mvpair, bitmanip, clz, ctz, cpop,
+			zicond, condmove, clmul, min, max, minu, maxu, rotate"))
+  "arcv_rmx100_ALU")
+
+(define_insn_reservation "arcv_rmx100_jmp_insn" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "branch, jump, call, jalr, ret, trap"))
+  "arcv_rmx100_ALU")
+
+; DIV insn: latency may be overridden by a define_bypass
+(define_insn_reservation "arcv_rmx100_div_insn" 35
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "idiv"))
+  "arcv_rmx100_DIV*35")
+
+; MPY insn: latency may be overridden by a define_bypass
+(define_insn_reservation "arcv_rmx100_mpy32_insn" 9
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "imul"))
+  "arcv_rmx100_MPY")
+
+(define_insn_reservation "arcv_rmx100_load_insn" 3
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "load"))
+  "arcv_rmx100_DMP,nothing*2")
+
+(define_insn_reservation "arcv_rmx100_store_insn" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "store,fpstore"))
+  "arcv_rmx100_DMP")
+
+;; FPU scheduling.  FIXME: This is based on the "fast" unit for now, the "slow"
+;; option remains to be implemented later (together with the -mfpu flag).
+
+(define_insn_reservation "arcv_rmx100_fpload_insn" 3
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fpload"))
+  "arcv_rmx100_DMP,nothing*2")
+
+(define_insn_reservation "arcv_rmx100_farith_insn" 2
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fadd,fcmp"))
+  "arcv_rmx100_FPU,nothing")
+
+(define_insn_reservation "arcv_rmx100_xfer" 1
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fmove,mtc,mfc,fcvt,fcvt_f2i,fcvt_i2f"))
+   "arcv_rmx100_FPU")
+
+(define_insn_reservation "arcv_rmx100_fmul_insn" 2
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fmul"))
+  "arcv_rmx100_FPU,nothing")
+
+(define_insn_reservation "arcv_rmx100_fmac_insn" 2
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fmadd"))
+  "arcv_rmx100_FPU,nothing")
+
+(define_insn_reservation "arcv_rmx100_fdiv_insn" 10
+  (and (eq_attr "tune" "arcv_rmx100")
+       (eq_attr "type" "fdiv,fsqrt"))
+  "arcv_rmx100_FPU")
+
+
+(define_bypass 1 "arcv_rmx100_mpy32_insn"
+  "arcv_rmx100_*" "arcv_mpy_1c_bypass_p")
+(define_bypass 2 "arcv_rmx100_mpy32_insn"
+  "arcv_rmx100_*" "arcv_mpy_2c_bypass_p")
+
+(define_bypass 9 "arcv_rmx100_div_insn" "arcv_rmx100_*" "arcv_mpy_1c_bypass_p")
+(define_bypass 9 "arcv_rmx100_div_insn" "arcv_rmx100_*" "arcv_mpy_2c_bypass_p")