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Merged
fogInSingularity merged 4 commits into from
Dec 22, 2025
Merged

Add bit slices to decode generator #2

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5980de4
add bit slices to decode (switches in generated code)
fogInSingularity Dec 22, 2025
a8ee5e8
update readme
fogInSingularity Dec 22, 2025
883ee75
minor emit_cpp.py change
fogInSingularity Dec 22, 2025
360fc8e
update readme
fogInSingularity Dec 22, 2025
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15 changes: 15 additions & 0 deletions README.md
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Expand Up @@ -5,6 +5,8 @@ risc-v simulator homework for compiler class. Implementation supports rv32imf_zb

- C++ compiler (with C++20 support)
- CMake (3.21+)
- Python (3.12+)
- Graphviz (optional)

## Build

Expand All @@ -18,3 +20,16 @@ cmake --build build
```bash
./build/riscv-sim.x <elf_bin> <args for elf_bin...>
```

## Notes

This project use generator to produce **instruction decoder** from the ISA description
(`src/isa/include/isa/isa_ext.inc`, the `MNEMONIC(name, mask, match)` table).
During the CMake build, the Python generator (`decode/pygen/gen_decoder.py`)
builds a **decision tree** over instruction bits/slices and emits `decode.cpp` as nested `if`/`switch` code.
You can select the decoder backend at configure time: `-DDECODE_BACKEND=generated` (default) or `-DDECODE_BACKEND=linear`.
Optionally, add `-DDECODE_EMIT_DOT=ON` to produce .dot representation of decision tree.

Example of generated decision tree for rv32i:

![generated decode tree](images/decode_tree.svg)
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