Add RISC-V scalar compatibility shim

[carlosqwqqwq]

Why

simdcomp currently supports x86/x64 through SSE/AVX and ARM through the in-tree neon128.h shim, but it has no clean portability path for riscv64. The core 128-bit kernels are already shared across architectures; the real blocker is that the build and headers still assume either x86 intrinsics or ARM NEON. As a result, a riscv64 target cannot select a conservative non-x86 compatibility layer even though the project's wider AVX2/AVX-512 files are already isolated behind x86-only feature macros.

What changed

• Added include/riscv128.h, a small self-contained scalar implementation of the subset of SSE2/SSSE3/SSE4.1 intrinsics that simdcomp actually uses.
• Updated include/portability.h so __riscv selects that shim instead of falling through to <x86intrin.h>, and exposed the minimal SSE feature macros required by the existing 128-bit source paths.
• Updated the public headers and source files that previously assumed “non-ARM means x86 headers” so RISC-V uses the shim path without pulling in <emmintrin.h> or <smmintrin.h>.
• Updated CMakeLists.txt to recognize riscv* targets, skip -march=native there, and inject __riscv=1 / __riscv_xlen=64 for simulated target validation when a real RISC-V cross toolchain is not present.
• Updated README.md to document that RISC-V currently uses a conservative scalar compatibility backend rather than RVV acceleration.

Verification

• Ran the native CMake/Ninja build successfully:
  • cmake -S . -B build-native -G Ninja -DSIMDCOMP_BUILD_TESTS=OFF -DSIMDCOMP_BUILD_EXAMPLES=OFF -DSIMDCOMP_BUILD_BENCHMARKS=OFF
  • cmake --build build-native --parallel 4
• Ran native tests successfully:
  • cmake -S . -B build-native-tests -G Ninja -DSIMDCOMP_BUILD_TESTS=ON -DSIMDCOMP_BUILD_EXAMPLES=OFF -DSIMDCOMP_BUILD_BENCHMARKS=OFF
  • cmake --build build-native-tests --parallel 4
  • ctest --test-dir build-native-tests --output-on-failure
• Ran the simulated riscv64 CMake configure/build successfully:
  • cmake -S . -B build-riscv-sim -G Ninja -DSIMDCOMP_BUILD_TESTS=OFF -DSIMDCOMP_BUILD_EXAMPLES=OFF -DSIMDCOMP_BUILD_BENCHMARKS=OFF -DCMAKE_SYSTEM_NAME=Linux -DCMAKE_SYSTEM_PROCESSOR=riscv64 -DCMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY -DSIMDCOMP_NATIVE=OFF -DCMAKE_EXPORT_COMPILE_COMMANDS=ON
  • cmake --build build-riscv-sim --parallel 4
• Confirmed the simulated riscv64 configure step reports RISC-V target detected; using scalar 128-bit compatibility shim.
• Checked build-riscv-sim/build.ninja and build-riscv-sim/compile_commands.json:
  • all library objects are compiled with -D__riscv=1 -D__riscv_xlen=64
  • there is no -march=native, -msse*, -mavx*, -march=arm*, -mfpu, or -mrvv
• Preprocessed include/portability.h with forced __riscv macros and confirmed it resolves through include/riscv128.h, while exposing __SSE2__, __SSSE3__, __SSE4_1__, and __SSE4_2__ but not __AVX2__ or __AVX512F__.
• Ran forced-__riscv smoke compiles successfully for:
  • src/simdbitpacking.c
  • src/simdintegratedbitpacking.c
  • src/simdcomputil.c
  • src/simdpackedsearch.c
  • src/simdpackedselect.c
• Verified a real riscv64 cross-build and runtime path in dockcross/linux-riscv64:
  • configured with CMAKE_C_COMPILER="$CC", CMAKE_SYSTEM_NAME=Linux, CMAKE_SYSTEM_PROCESSOR=riscv64, CMAKE_TRY_COMPILE_TARGET_TYPE=STATIC_LIBRARY, SIMDCOMP_BUILD_TESTS=ON, SIMDCOMP_BUILD_EXAMPLES=ON, SIMDCOMP_BUILD_BENCHMARKS=OFF, and SIMDCOMP_NATIVE=OFF;
  • built example, unit, and unit_chars successfully with /usr/xcc/riscv64-unknown-linux-gnu/bin/riscv64-unknown-linux-gnu-gcc.
• Verified the produced binary is a real RISC-V executable:
  • file reports ELF 64-bit LSB executable, UCB RISC-V, RVC, double-float ABI for example;
  • readelf -h reports Machine: RISC-V.
• Verified the real riscv64 build does not rely on host ISA tuning flags:
  • build.ninja contains no -march=native, -msse*, -mavx*, -mfpu=neon, or arm_neon.
• Verified the archived library does not expose AVX code on RISC-V:
  • libsimdcomp.a still contains avxbitpacking.c.o and avx512bitpacking.c.o members, but riscv64-unknown-linux-gnu-nm finds no avx symbols in the archive.
• Ran the resulting binaries under qemu-riscv64 successfully:
  • example completed the compression/decompression demos and printed Code works!;
  • unit completed and printed All tests OK!;
  • unit_chars completed and printed Code looks good.

Notes

This is a conservative portability patch. It does not add RVV or any dedicated RISC-V vector optimization backend. The goal is to let riscv64 build and validate cleanly against the existing 128-bit kernel API without leaking x86-specific headers or -march=native assumptions into the RISC-V path. Validation now includes a real riscv64 cross-build and qemu-riscv64 execution of the example and unit-test binaries, but it still does not include RVV coverage or real RISC-V hardware testing.