update main branch from rc1

.gitignore

@@ -0,0 +1,8 @@
+.DS_Store
+*.vscode
+venv/
+gen/
+bd*/
+logs
+**/__pycache__/
+./openocd.cfg

README.md

@@ -1,4 +1,30 @@
-# Embench DSP Suite
+# Embench™ DSP: Open Signal Processing Benchmarks for Embedded Platforms
 
-This is currently a placeholder for a suite of tests aimed at digital signal
-processors with up to 1MB of memory.
+## Stable benchmark versions
+
+The following git tags may be used to select the version of the repository for a stable release.
+
+- `embench-dsp-1.0`
+
+## Using the benchmarks
+
+The benchmarks can be used to yield a single consistent score for the
+performance of a platform and its compiler tool chain.  The mechanism for this is described in the [user manual](./doc/README.md).
+
+## Structure of the repository
+
+The top level directory contains Python scripts to build and execute the benchmarks. The following are the key top level directories.
+
+- [`examples`](./examples): containing examples for Embench build configurations for different boards.
+
+- [`doc`](./doc): The user manual for Embench-DSP.
+
+- [`golden-ref`](./golden-ref): Scripts to generate the DSP test data (input, output, coefficients, etc.). Parameterized number of samples to support more than one benchmark in some cases.
+
+- [`lib`](./lib): The library source of the DSP functions, modified from the CMSIS DSP Library.
+
+- [`src`](./src): The top-level source for the benchmarks, one directory per benchmark.
+
+- [`support`](./support): The generic wrapper code and helper functions for benchmarks.
+
+- [`pylib`](./pylib): Support code for the python scripts.

baseline-data/size.json

@@ -0,0 +1,62 @@
+{
+  "biquad_cascade_df2T_f32_sos3_n1" : {
+    "text" : 29816,
+    "rodata" : 1056,
+    "data" : 2212,
+    "bss" : 412
+  },
+  "biquad_cascade_df2T_f32_sos3_n128" : {
+    "text" : 29816,
+    "rodata" : 1056,
+    "data" : 3228,
+    "bss" : 924
+  },
+  "dct4_2048_f32" : {
+    "text" : 33600,
+    "rodata" : 45648,
+    "data" : 18100,
+    "bss" : 16772
+  },
+  "dct4_512_f32" : {
+    "text" : 33600,
+    "rodata" : 12208,
+    "data" : 5812,
+    "bss" : 4484
+  },
+  "fir_f32_taps256_n1" : {
+    "text" : 29968,
+    "rodata" : 1048,
+    "data" : 3772,
+    "bss" : 1412
+  },
+  "fir_f32_taps256_n128" : {
+    "text" : 29968,
+    "rodata" : 1048,
+    "data" : 4788,
+    "bss" : 2428
+  },
+  "lms_f32_taps256_n1" : {
+    "text" : 30104,
+    "rodata" : 1048,
+    "data" : 4796,
+    "bss" : 3468
+  },
+  "lms_f32_taps256_n128" : {
+    "text" : 30104,
+    "rodata" : 1048,
+    "data" : 6324,
+    "bss" : 4988
+  },
+  "rfft2048_f32" : {
+    "text" : 33208,
+    "rodata" : 21048,
+    "data" : 18100,
+    "bss" : 8580
+  },
+  "rfft512_f32" : {
+    "text" : 33208,
+    "rodata" : 6040,
+    "data" : 5812,
+    "bss" : 2436
+  }
+}

baseline-data/speed.json

@@ -0,0 +1,12 @@
+{
+  "biquad_cascade_df2T_f32_sos3_n1" : 10,
+  "biquad_cascade_df2T_f32_sos3_n128" : 510,
+  "dct4_2048_f32" : 19296,
+  "dct4_512_f32" : 4536,
+  "fir_f32_taps256_n1" : 244,
+  "fir_f32_taps256_n128" : 18651,
+  "lms_f32_taps256_n1" : 454,
+  "lms_f32_taps256_n128" : 47404,
+  "rfft2048_f32" : 9704,
+  "rfft512_f32" : 2131
+}