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Updated name of user project inside wrapper #9

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Updated name of user project inside wrapper #9

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8 changes: 4 additions & 4 deletions verilog/rtl/user_project_wrapper.v
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Original file line number Diff line number Diff line change
Expand Up @@ -95,11 +95,11 @@ module user_project_wrapper #(
generate
for (i = 0; i < USER_PROJECTS; i = i + 1) begin : user_projects
if (i % 2 == 0)
user_project #(
user_project_wrapper_mini4 #(
`ifndef PnR
.COUNT_STEP(2 * i + 1)
`endif
) user_project (
) user_project_wrapper_mini4 (
`ifdef USE_POWER_PINS
.VPWR(vccd2), // User area 1 1.8V supply
.VGND(vssd2), // User area 1 digital ground
Expand Down Expand Up @@ -139,11 +139,11 @@ module user_project_wrapper #(
.user_irq(proj_user_irq[i])
);
else
user_project #(
user_project_wrapper_mini4 #(
`ifndef PnR
.COUNT_STEP(2 * i + 1)
`endif
) user_project (
) user_project_wrapper_mini4 (
`ifdef USE_POWER_PINS
.VPWR(vccd1), // User area 1 1.8V supply
.VGND(vssd1), // User area 1 digital ground
Expand Down