Move module documentation from score repo

MODULE.bazel

@@ -89,11 +89,17 @@ bazel_dep(name = "openssl", version = "3.5.5.bcr.4")
 
 ## Custom Module Loading
 
-bazel_dep(name = "score_docs_as_code", version = "4.0.3", dev_dependency = True)
+bazel_dep(name = "score_docs_as_code", version = "4.2.0", dev_dependency = True)
 bazel_dep(name = "score_process", version = "1.5.4", dev_dependency = True)
 bazel_dep(name = "score_tooling", version = "1.2.0", dev_dependency = True)
 bazel_dep(name = "score_platform", version = "0.5.5", dev_dependency = True)
 
+git_override(
+    module_name = "score_platform",
+    commit = "ef5a88b25f2e32eafeaadbef2e784aa3b7c2a18d",
+    remote = "https://github.com/eclipse-score/score",
+)
+
 ## Configure the python toolchain
 
 bazel_dep(name = "rules_python", version = "1.8.3", dev_dependency = True)

docs/architecture/chklst_arc_inspection.rst

@@ -0,0 +1,185 @@
+..
+   # *******************************************************************************
+   # Copyright (c) 2025 Contributors to the Eclipse Foundation
+   #
+   # See the NOTICE file(s) distributed with this work for additional
+   # information regarding copyright ownership.
+   #
+   # This program and the accompanying materials are made available under the
+   # terms of the Apache License Version 2.0 which is available at
+   # https://www.apache.org/licenses/LICENSE-2.0
+   #
+   # SPDX-License-Identifier: Apache-2.0
+   # *******************************************************************************
+
+
+Architecture Inspection Checklist
+=================================
+
+.. document:: Baselibs Architecture Inspection Checklist
+   :id: doc__baselibs_arc_inspection
+   :status: valid
+   :safety: ASIL_B
+   :security: YES
+   :realizes: wp__sw_arch_verification
+
+Purpose
+-------
+
+The purpose of the software architecture checklist is to ensure that the design meets the criteria and quality as
+defined per S-CORE processes and guidelines for feature and component architectural design elements.
+It helps to check the compliance with requirements, identify errors or inconsistencies, and ensure adherence to best
+practices.
+The checklist guides evaluation of the architecture design, identifies potential problems, and aids in
+communication and documentation of architectural decisions to stakeholders.
+
+Conduct
+-------
+
+As described in the concept :need:`doc_concept__wp_inspections` the following "inspection roles" are expected to be filled:
+
+- content responsible (author): `<https://github.com/4og>`_
+- reviewer: `<https://github.com/aschemmel-tech>`_
+- moderator: only needed for conflict resolution between author and reviewers, is the safety manager, security manager or quality manager called in as a reviewer (can be derived from version mgt tool)
+
+Checklist
+---------
+
+It is mandatory to fill in the "passed" column with "yes" or "no" for each checklist item and additionally to add in the remarks why it is passed or not passed.
+In case of "no" an issue link to the issue tracking system has to be added in the last column (if not solved in the same issue).
+See also :need:`doc_concept__wp_inspections` for further information about reviews in general and inspection in particular.
+
+.. list-table:: Architecture Design Review Checklist
+    :header-rows: 1
+
+    * - Review Id
+      - Acceptance criteria
+      - Guidance
+      - passed
+      - Remarks
+      - Issue link
+    * - ARC_01_01
+      - Is the traceability from software architectural elements to requirements, and other level architectural
+        elements (e.g. component to interface) established according to the "Relations between the architectural elements" as described in :need:`doc_concept__arch_process`?
+      - Trace should be checked automatically by tool support in the future. It will be removed from the checklist once the requirement (:need:`Correlations of the architectural building blocks <gd_req__arch_build_blocks_corr>`) is implemented. Refer to `Tool Requirements <https://eclipse-score.github.io/docs-as-code/main/internals/requirements/requirements.html>`_ for the current status.
+      - NO
+      - Several functional feature requirements are not linked to the baselibs feature architecture.
+      - `#2265 <https://github.com/eclipse-score/score/issues/2265>`_
+    * - ARC_01_02
+      - If the architectural element is related to any supplier manuals (incl. safety and security)
+        are the relevant parts covered?
+      - If the architecture makes use of supplied elements, their manuals (like safety) have to be considered (i.e. its provided functionality matches the expectation and assumptions are fulfilled). Note that in case of safety component this means that assumed Technical Safety Requirements and AoUs of the safety manual are covered.
+      - YES
+      - Baselibs uses OS. S-CORE's reference OS safety manual was considered during development, but cannot be published in this open source project
+      -
+    * - ARC_01_03
+      - Is the architectural element traceable to the lower level artifacts as defined by the workproduct traceability?
+      - Will be removed from checklist once the requirement (:need:`Correlations of the architectural building blocks <gd_req__arch_build_blocks_corr>`) is implemented by automated tool check. See `Tool Requirements <https://eclipse-score.github.io/docs-as-code/main/internals/requirements/requirements.html>`_.
+        Details of possible linking can be depicted from `traceability concept <https://eclipse-score.github.io/process_description/main/general_concepts/score_traceability_concept.html>`_
+      - YES
+      - Baselibs feature architecture includes logic interfaces, these can be used to link to components (see static view :need:`feat_arc_sta__baselibs__static_view_arch`)
+      -
+    * - ARC_02_01
+      - Is the software architecture design compliant with the (overall) feature architecture?
+      - On component level check against the feature architecture, on feature level check other features with common components used.
+      - YES
+      - Shared module is the OS, which is designed to work with multiple components using it.
+      -
+    * - ARC_02_02
+      - Is appropriate and comprehensible operation/interface naming present in the architectural design?
+      - Check :need:`gd_guidl__arch_design`
+      - YES
+      - Interfaces and operations names are abstract but sufficient for understanding.
+      -
+    * - ARC_02_03
+      - Are correctness of data flow and control flow within the architectural elements considered?
+      - E.g. examine definitions, transformations, integrity, and interaction of data; check error handling, data
+        exchange between elements, correct response to inputs and documented decision making.
+        Note: consistency is ensured by the process/tooling, by defining each interface only once.
+      - YES
+      - There is no control/data flow between baselibs components (each of it is stand-alone), so no sequence diagram needed.
+      -
+    * - ARC_02_04
+      - Are the interfaces between the software architectural element and other architectural elements well-defined?
+      - Check if the interface reacts on non-defined behavior or errors; can established protocols be used; are the
+        interfaces for inputs, outputs, error codes documented; is loose coupling considered and only limited exposure;
+        can unit or integration test be written against the interface; data amount transferred; no sensitive data
+        exposure;
+      - NO
+      - Errors are generally managed by the "Result" component (ok)
+        If an operation is an input or an output is not shown (nok)
+        Libraries are split in logical way, enable testing, data amount and sensitivity is not an issue. Maybe with the exception of JSON - add a AoU here?
+      - `#2265 <https://github.com/eclipse-score/score/issues/2265>`_
+    * - ARC_02_05
+      - Does the software architectural element consider the timing constraints (from the parent requirement)?
+      - If there are hard requirements on the timing a programming time estimation should be performed and also
+        deadline supervision considered.
+      - YES
+      - As the functionalities are quite small, timing should not be a problem. No requirements on timing for baselibs.
+      -
+    * - ARC_02_06
+      - Is the documentation of the software architectural element, including textual and graphical descriptions
+        (e.g., UML diagrams), comprehensible and complete?
+      - Use of semi-formal notation is expected for architectural elements with an allocated ASIL level.
+        Is the architecture template correctly filled?
+      - NO
+      - Architecture template: Requirements section missing, but this is covered by Static View linking, Module View not needed (same as Feature Static View) (ok)
+        Semi-Formal Notation used (ok)
+        Mismatch between libraries mentioned in "Description" and the ones depicted in Static View (this also does not match with the 0.5 planning/release note) and also not matching feature request https://eclipse-score.github.io/score/main/features/baselibs/index.html (nok)
+      - `#2265 <https://github.com/eclipse-score/score/issues/2265>`_
+    * - ARC_03_01
+      - Is the architectural element modular and encapsulated?
+      - Check e.g. that only minimal interfaces are used. Design should be object oriented. Interfaces and interactions are clearly defined. Usage of access types (private, protected) properly set. Limited global variables.
+      - YES
+      - small functionality
+      -
+    * - ARC_03_02
+      - Is the suitability of the software architecture for future modifications and maintainability considered?
+      - Check for e.g. loose coupling, separation of concerns, high cohesion, versioning strategy for interfaces,
+        decision records, use of established design patterns.
+      - YES
+      - Nothing which can be seen in the architecture documentation speaks against this.
+      -
+    * - ARC_03_03
+      - Are simplicity and avoidance of unnecessary complexity present in the software architecture?
+      - Indicators for complexity are: number of use cases (corresponding to dynamic diagrams)
+        allocated to single design element, number of interfaces and operations in an interface,
+        function parameters, global variables, complex types, limited comprehensibility.
+
+        Note: If the "number" above exceeds "3" a design rationale is mandatory (for all types)
+      - YES
+      - Baselibs is just a big container for globally shared library functions - thus offers a lot of (unconnected) interfaces.
+      -
+    * - ARC_03_04
+      - Is the software architecture design following best practices and design principles?
+      - Refer to architectural guidelines and recommendations within the project documentation.
+      - YES
+      - Guideline :need:`gd_guidl__arch_design` is followed, template usage checked in ARC_02_06, some design principles already checked in ARC_03_02, no additional recommendations in the project's PMP
+      -
+
+.. attention::
+    The above checklist entries must be filled according to your feature architecture in scope.
+
+Note: If a Review ID is not applicable for your architecture, then state ""n/a" in status and comment accordingly in remarks.
+
+The following static views in "valid" state and with "inspected" tag set are in the scope of this inspection:
+
+.. needtable::
+   :filter: "baselibs" in docname and "architecture" in docname and docname is not None and status == "valid"
+   :style: table
+   :types: feat_arc_sta
+   :tags: baselibs
+   :columns: id;status;tags
+   :colwidths: 25,25,25
+   :sort: title
+
+and the following dynamic views:
+
+.. needtable::
+   :filter: "baselibs" in docname and "architecture" in docname and docname is not None and status == "valid"
+   :style: table
+   :types: feat_arc_dyn
+   :tags: baselibs
+   :columns: id;status;tags
+   :colwidths: 25,25,25
+   :sort: title

docs/architecture/index.rst

@@ -0,0 +1,122 @@
+..
+   # *******************************************************************************
+   # Copyright (c) 2025 Contributors to the Eclipse Foundation
+   #
+   # See the NOTICE file(s) distributed with this work for additional
+   # information regarding copyright ownership.
+   #
+   # This program and the accompanying materials are made available under the
+   # terms of the Apache License Version 2.0 which is available at
+   # https://www.apache.org/licenses/LICENSE-2.0
+   #
+   # SPDX-License-Identifier: Apache-2.0
+   # *******************************************************************************
+.. _baselibs_architecture:
+
+Architecture
+=====================
+
+.. document:: Baselibs Architecture
+   :id: doc__baselibs_architecture
+   :status: valid
+   :safety: ASIL_B
+   :security: YES
+   :realizes: wp__feature_arch
+
+Overview
+--------
+
+A brief overview of Baselibs is described :ref:`baselibs_feature`.
+
+Description
+-----------
+
+A detailed description of the Baselibs module requirements is located :need:`feat_req__baselibs__core_utilities`.
+
+The Baselibs module provides foundational software utilities, safety mechanisms and robust infrastructure components. It comprises essential libraries organized into functional categories:
+
+**Core Utility Libraries**
+
+- **bitmanipulation**: Utilities for bit manipulation operations
+- **containers**: Specialized container implementations including ``DynamicArray`` and intrusive linked lists
+- **utils**: Reusable utilities including type traits, mathematical utilities and string manipulation helpers
+
+**Threading and Concurrency**
+
+- **concurrency**: Interface for parallel execution of C++ callables with thread pool management
+
+**Data Processing and Serialization**
+
+- **json**: JSON abstraction layer with pluggable backend support
+- **static_reflection_with_serialization**: Binary serialization/deserialization with compile-time type reflection
+
+**File System and I/O Operations**
+
+- **filesystem**: Filesystem manipulation library similar to ``std::filesystem``
+
+**Memory Management**
+
+- **memory**: Memory handling utilities for safety-critical applications with shared memory support
+
+**Operating System Abstraction**
+
+- **os**: OS Abstraction Layer (OSAL) for POSIX-like systems including Linux and QNX
+
+**Error Handling and Safety**
+
+- **result**: Error handling without exceptions, conforming to C++23 ``std::expected`` specification
+- **safecpp**: Safety framework including exception prevention and overflow-safe implementations
+
+**Modern C++ Extensions and Logging**
+
+- **futurecpp**: C++14 Standard Library extensions with backported components
+- **mw::log**: Logging library for automotive systems with structured logging and multiple backends
+
+These libraries form an integrated ecosystem designed for code reuse, consistency and safety throughout the platform.
+
+
+
+Rationale Behind Architecture Decomposition
+*******************************************
+
+The decomposition of Baselibs into modular libraries is motivated by the need for code reuse, maintainability and consistent APIs across the platform. This approach enables platform modules to leverage common infrastructure, reduces duplication and supports safety and security requirements.
+
+Static Architecture
+-------------------
+
+.. feat_arc_sta:: Baselibs Static View
+   :id: feat_arc_sta__baselibs__static_view_arch
+   :security: YES
+   :safety: ASIL_B
+   :status: valid
+   :fulfils: feat_req__baselibs__core_utilities
+   :includes: logic_arc_int__baselibs__json, logic_arc_int__baselibs__memory_shared, logic_arc_int__baselibs__result, logic_arc_int__baselibs__bit_manipulation, logic_arc_int__baselibs__bit_mask_operator, logic_arc_int__baselibs__dynamic_array, logic_arc_int__baselibs__intrusive_list, logic_arc_int__baselibs__filesystem, logic_arc_int__baselibs__utils_base64, logic_arc_int__baselibs__utils_scoped_op, logic_arc_int__baselibs__promise, logic_arc_int__baselibs__future, logic_arc_int__baselibs__shared_future, logic_arc_int__baselibs__executor, logic_arc_int__baselibs__task, logic_arc_int__baselibs__task_result, logic_arc_int__baselibs__synchronized_queue, logic_arc_int__baselibs__condition_variable, logic_arc_int__baselibs__aborts_upon_ex, logic_arc_int__baselibs__coverage_termination, logic_arc_int__baselibs__safemath, logic_arc_int__baselibs__safeatomics, logic_arc_int__baselibs__scoped_function, logic_arc_int__baselibs__string_view
+   :tags: inspected
+   :belongs_to: feat__baselibs
+
+   .. needarch::
+      :scale: 50
+      :align: center
+
+      {{ draw_feature(need(), needs) }}
+
+.. feat_arc_dyn:: Baselibs Dynamic View
+   :id: feat_arc_dyn__baselibs__dynamic_view_arch
+   :security: YES
+   :safety: ASIL_B
+   :status: valid
+   :fulfils: feat_req__baselibs__core_utilities
+   :belongs_to: feat__baselibs
+
+   not needed, simple caller/callee sequence
+
+Logical Interfaces
+------------------
+
+The Baselibs feature exposes the following logical interfaces:
+
+.. needtable::
+   :style: table
+   :columns: title;id;status
+   :sort: title
+   :filter: id in ['logic_arc_int__baselibs__json', 'logic_arc_int__baselibs__memory_shared', 'logic_arc_int__baselibs__result', 'logic_arc_int__baselibs__bit_manipulation', 'logic_arc_int__baselibs__bit_mask_operator', 'logic_arc_int__baselibs__dynamic_array', 'logic_arc_int__baselibs__intrusive_list', 'logic_arc_int__baselibs__filesystem', 'logic_arc_int__baselibs__utils_base64', 'logic_arc_int__baselibs__utils_scoped_op', 'logic_arc_int__baselibs__promise', 'logic_arc_int__baselibs__future', 'logic_arc_int__baselibs__shared_future', 'logic_arc_int__baselibs__executor', 'logic_arc_int__baselibs__task', 'logic_arc_int__baselibs__task_result', 'logic_arc_int__baselibs__synchronized_queue', 'logic_arc_int__baselibs__condition_variable', 'logic_arc_int__baselibs__aborts_upon_ex', 'logic_arc_int__baselibs__coverage_termination', 'logic_arc_int__baselibs__safemath', 'logic_arc_int__baselibs__safeatomics', 'logic_arc_int__baselibs__scoped_function', 'logic_arc_int__baselibs__string_view']

docs/bitmanipulation/docs/architecture/chklst_arc_inspection.rst

@@ -0,0 +1,47 @@
+..
+   # *******************************************************************************
+   # Copyright (c) 2025 Contributors to the Eclipse Foundation
+   #
+   # See the NOTICE file(s) distributed with this work for additional
+   # information regarding copyright ownership.
+   #
+   # This program and the accompanying materials are made available under the
+   # terms of the Apache License Version 2.0 which is available at
+   # https://www.apache.org/licenses/LICENSE-2.0
+   #
+   # SPDX-License-Identifier: Apache-2.0
+   # *******************************************************************************
+
+
+.. document:: Bitmanipulation Architecture Inspection Checklist
+   :id: doc__bitmanipulation_arc_inspection
+   :status: valid
+   :safety: ASIL_B
+   :security: YES
+   :realizes: wp__sw_arch_verification
+
+Architecture Inspection Checklist
+=================================
+
+No need for component architecture inspection, as there is no additional information as in the
+feature architecture :need:`doc__baselibs_architecture` and this is to be inspected.
+
+The following static views in "valid" state and with "inspected" tag set are in the scope of this inspection:
+
+.. needtable::
+   :filter: docname is not None and "bitmanipulation" in docname and "architecture" in docname and status == "valid"
+   :style: table
+   :types: comp_arc_sta
+   :columns: id;status;tags
+   :colwidths: 25,25,25
+   :sort: title
+
+and the following dynamic views:
+
+.. needtable::
+   :filter: "bitmanipulation" in docname and "architecture" in docname and docname is not None and status == "valid"
+   :style: table
+   :types: comp_arc_dyn
+   :columns: id;status;tags
+   :colwidths: 25,25,25
+   :sort: title