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2 changes: 1 addition & 1 deletion regression/verilog/system-functions/past1.aig.desc
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
CORE
past1.sv
--aig
^\[main\.p0\] ##0 \(\$past\(main\.counter, 0\)\) == 0: FAILURE: property not supported by netlist BMC engine$
^\[main\.p0\] ##0 \$past\(main\.counter, 0\) == 0: FAILURE: property not supported by netlist BMC engine$
^EXIT=10$
^SIGNAL=0$
--
2 changes: 1 addition & 1 deletion regression/verilog/system-functions/past1.bdd.desc
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
CORE
past1.sv
--bdd
^\[main\.p0\] ##0 \(\$past\(main\.counter, 0\)\) == 0: FAILURE: property not supported by BDD engine$
^\[main\.p0\] ##0 \$past\(main\.counter, 0\) == 0: FAILURE: property not supported by BDD engine$
^EXIT=10$
^SIGNAL=0$
--
2 changes: 1 addition & 1 deletion regression/verilog/system-functions/past2.desc
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
CORE
past2.sv
--bdd
^\[main\.p0\] always \(main\.counter == 0 \|-> \(\$past\(main\.counter, 1\)\) == 0\): FAILURE: property not supported by BDD engine$
^\[main\.p0\] always \(main\.counter == 0 \|-> \$past\(main\.counter, 1\) == 0\): FAILURE: property not supported by BDD engine$
^EXIT=10$
^SIGNAL=0$
--
Expand Down
12 changes: 6 additions & 6 deletions src/verilog/expr2verilog.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -354,7 +354,7 @@ expr2verilogt::convert_function_call(const function_call_exprt &src)

dest+=")";

return {verilog_precedencet::MIN, dest};
return {verilog_precedencet::MEMBER, dest};
}

/*******************************************************************\
Expand Down Expand Up @@ -675,19 +675,19 @@ Function: expr2verilogt::convert_typecast

\*******************************************************************/

expr2verilogt::resultt expr2verilogt::convert_typecast(
const typecast_exprt &src,
verilog_precedencet &precedence)
expr2verilogt::resultt
expr2verilogt::convert_typecast(const typecast_exprt &src)
{
if(src.operands().size()==1)
{
//const typet &from=src.op0().type();
//const typet &to=src.type();

// just ignore them for now
return {precedence, convert_rec(src.op()).s};
return convert_rec(src.op());
}

verilog_precedencet precedence;
return convert_norep(src, precedence);
}

Expand Down Expand Up @@ -1380,7 +1380,7 @@ expr2verilogt::resultt expr2verilogt::convert_rec(const exprt &src)
to_bitnot_expr(src), "~", precedence = verilog_precedencet::NOT);

else if(src.id()==ID_typecast)
return convert_typecast(to_typecast_expr(src), precedence);
return convert_typecast(to_typecast_expr(src));

else if(src.id()==ID_and)
return convert_binary(
Expand Down
2 changes: 1 addition & 1 deletion src/verilog/expr2verilog_class.h
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ class expr2verilogt

resultt convert_constant(const constant_exprt &, verilog_precedencet &);

resultt convert_typecast(const typecast_exprt &, verilog_precedencet &);
resultt convert_typecast(const typecast_exprt &);

resultt
convert_concatenation(const concatenation_exprt &, verilog_precedencet);
Expand Down
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