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Verilog: zero_extend now considers genvar #792

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Merged
tautschnig merged 1 commit into from
Oct 31, 2024
Merged

Verilog: zero_extend now considers genvar #792

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3 changes: 1 addition & 2 deletions regression/verilog/system-functions/low1.desc
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Original file line number Diff line number Diff line change
@@ -1,9 +1,8 @@
KNOWNBUG
CORE broken-smt-backend
low1.sv
--module main --bound 0
^EXIT=0$
^SIGNAL=0$
--
^warning: ignoring
--
This yields an error in the typechecker.
5 changes: 3 additions & 2 deletions src/verilog/verilog_typecheck_expr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2351,8 +2351,9 @@ Function: zero_extend

static exprt zero_extend(const exprt &expr, const typet &type)
{
auto old_width = expr.type().id() == ID_bool
? 1
auto old_width = expr.type().id() == ID_bool ? 1
: expr.type().id() == ID_integer
? 32
: to_bitvector_type(expr.type()).get_width();

// first make unsigned
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