Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 4 additions & 4 deletions src/verilog/verilog_elaborate.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -804,15 +804,15 @@ void verilog_typecheckt::collect_symbols(
{
auto &parameter_decl = to_verilog_parameter_decl(module_item);
collect_symbols(parameter_decl.type());
for(auto &decl : parameter_decl.declarations())
collect_symbols(parameter_decl.type(), decl);
for(auto &declarator : parameter_decl.declarators())
collect_symbols(parameter_decl.type(), declarator);
}
else if(module_item.id() == ID_local_parameter_decl)
{
auto &localparam_decl = to_verilog_local_parameter_decl(module_item);
collect_symbols(localparam_decl.type());
for(auto &decl : localparam_decl.declarations())
collect_symbols(localparam_decl.type(), decl);
for(auto &declarator : localparam_decl.declarators())
collect_symbols(localparam_decl.type(), declarator);
}
else if(module_item.id() == ID_decl)
{
Expand Down
12 changes: 6 additions & 6 deletions src/verilog/verilog_expr.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -146,19 +146,19 @@ static void dependencies_rec(
else if(module_item.id() == ID_parameter_decl)
{
auto &parameter_decl = to_verilog_parameter_decl(module_item);
for(auto &decl : parameter_decl.declarations())
for(auto &declarator : parameter_decl.declarators())
{
dependencies_rec(decl.type(), dest);
dependencies_rec(decl.value(), dest);
dependencies_rec(declarator.type(), dest);
dependencies_rec(declarator.value(), dest);
}
}
else if(module_item.id() == ID_local_parameter_decl)
{
auto &localparam_decl = to_verilog_local_parameter_decl(module_item);
for(auto &decl : localparam_decl.declarations())
for(auto &declarator : localparam_decl.declarators())
{
dependencies_rec(decl.type(), dest);
dependencies_rec(decl.value(), dest);
dependencies_rec(declarator.type(), dest);
dependencies_rec(declarator.value(), dest);
}
}
else if(module_item.id() == ID_decl)
Expand Down
9 changes: 5 additions & 4 deletions src/verilog/verilog_expr.h
Original file line number Diff line number Diff line change
Expand Up @@ -680,6 +680,7 @@ class verilog_declaratort : public exprt

using verilog_declaratorst = std::vector<verilog_declaratort>;

/// a SystemVerilog parameter declaration
class verilog_parameter_declt : public verilog_module_itemt
{
public:
Expand All @@ -690,12 +691,12 @@ class verilog_parameter_declt : public verilog_module_itemt
using declaratort = verilog_declaratort;
using declaratorst = verilog_declaratorst;

const declaratorst &declarations() const
const declaratorst &declarators() const
{
return (const declaratorst &)operands();
}

declaratorst &declarations()
declaratorst &declarators()
{
return (declaratorst &)operands();
}
Expand Down Expand Up @@ -725,12 +726,12 @@ class verilog_local_parameter_declt : public verilog_module_itemt
using declaratort = verilog_declaratort;
using declaratorst = verilog_declaratorst;

const declaratorst &declarations() const
const declaratorst &declarators() const
{
return (const declaratorst &)operands();
}

declaratorst &declarations()
declaratorst &declarators()
{
return (declaratorst &)operands();
}
Expand Down
9 changes: 5 additions & 4 deletions src/verilog/verilog_parameterize_module.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -43,8 +43,8 @@ verilog_typecheckt::get_parameter_declarators(

for(auto &item : module_items)
if(item.id() == ID_parameter_decl)
for(auto &decl : to_verilog_parameter_decl(item).declarations())
declarators.push_back(decl);
for(auto &declarator : to_verilog_parameter_decl(item).declarators())
declarators.push_back(declarator);

return declarators;
}
Expand Down Expand Up @@ -173,15 +173,16 @@ void verilog_typecheckt::set_parameter_values(
for(auto &module_item : module_items)
if(module_item.id() == ID_parameter_decl)
{
for(auto &decl : to_verilog_parameter_decl(module_item).declarations())
for(auto &declarator :
to_verilog_parameter_decl(module_item).declarators())
{
if(p_it!=parameter_values.end())
{
DATA_INVARIANT(p_it != parameter_values.end(), "have enough parameter values");

// only overwrite when actually assigned
if(p_it->is_not_nil())
decl.value() = *p_it;
declarator.value() = *p_it;

p_it++;
}
Expand Down
Loading