KNOWNBUG test for parameter without default value #1415
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tautschnig
approved these changes
Nov 17, 2025
| module main; | ||
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| sub #(123) submodule(); | ||
| sub #(8'd123) submodule(); |
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How is this change related to the KNOWNBUG test?
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Unrelated, dropping
SystemVerilog 1800-2017 allows module parameter ports without default value.
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SystemVerilog 1800-2017 allows module parameter ports without default value.