Verilog: KNOWNBUG test for unconnected module input ports#1322
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tautschnig merged 1 commit intomainfrom Oct 15, 2025
Merged
Verilog: KNOWNBUG test for unconnected module input ports#1322tautschnig merged 1 commit intomainfrom
tautschnig merged 1 commit intomainfrom
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Would you mind adding a sentence stating what is going wrong here?
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