SystemVerilog: grammar for config declarations#1314
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tautschnig merged 1 commit intomainfrom Oct 12, 2025
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This adds the grammar for parsing SystemVerilog configuration declarations (1800-2017 Sec 33). There are no production rules, i.e., the configurations are ignored.
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This adds the grammar for parsing SystemVerilog configuration declarations (1800-2017 Sec 33). There are no production rules, i.e., the configurations are ignored.