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Agreed to be a added as a new project |
bensternthal
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Apr 30, 2024
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This pr needs a few minor changes before merging, note this is due to updates we have made since this was filed:
- This file should live in this directory
projects/project-data-files - Two items were added to the template:
communication_channels: "List project communication channels e.g. Slack, IRC, Mailing Lists"
financial_sponsorship: "Y/N - is there existing financial sponsorship of the project"```
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
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done - moved to data-files dir and updated to new template |
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Synlig is now part of SV tools, closing. |
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This project (source code wise) is already in CHIPS Alliance, but originally was a part of yosys-f4pga-plugins. It has later been extracted as a separate repo and renamed to Systemverilog Netlist Generator (Synlig) as the tool targets both FPGAs and ASICs. This application is formally separating it from F4PGA that is meant FPGA only.