-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathComp.cr.mti
More file actions
557 lines (484 loc) · 30.1 KB
/
Comp.cr.mti
File metadata and controls
557 lines (484 loc) · 30.1 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/myreg.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/myreg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity myreg
-- Compiling architecture regbehav of myreg
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/PC.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\CarryMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity carryMux
-- Compiling architecture behav of carryMux
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/HalfAdder.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/HalfAdder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity HalfAdder
-- Compiling architecture dataflow of HalfAdder
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/OverFlow.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/OverFlow.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity overflow
-- Compiling architecture behaviour of overflow
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/RSCPU.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\RSCPU.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package ATTRIBUTES
-- Loading package std_logic_misc
-- Compiling entity RSCPU
-- Compiling architecture Idontknow of RSCPU
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/AdderGroup.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/AdderGroup.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity AdderGroup
-- Compiling architecture struct of AdderGroup
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/BTLOGIC.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/BTLOGIC.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BTLOGIC
-- Compiling architecture behavioural of BTLOGIC
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/CarryMux.vhd} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\CarryMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity carryMux
-- Compiling architecture behav of carryMux
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/CarryFlag.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\CarryFlag.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity Cry
-- Compiling architecture behaviour of Cry
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/Fulladder.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/Fulladder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity FullAdder
-- Compiling architecture structural of FullAdder
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/MucBus.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/MucBus.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MuxBus
-- Compiling architecture behav of MuxBus
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicSeq.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\MicSeq.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity micSeq
-- Compiling architecture struct of micSeq
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/multiplexer.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/multiplexer.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux1
-- Compiling architecture behavioral of mux1
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MICOPOUT.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MICOPOUT.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package microoperations
-- Compiling entity MICOPOUT
-- Compiling architecture struct of MICOPOUT
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/mux3.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/mux3.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux3
-- Compiling architecture behavioral of mux3
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/multiplexer2.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/multiplexer2.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2
-- Compiling architecture behavioral of mux2
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MucBus.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MucBus.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MuxBus
-- Compiling architecture behav of MuxBus
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicMem.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\MicMem.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MicMem
-- Compiling architecture behav of MicMem
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/memory.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/memory.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity sync_ram
-- Compiling architecture RTL of sync_ram
** Warning: D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/memory.vhd(66): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/CarryFlag.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/CarryFlag.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity Cry
-- Compiling architecture behaviour of Cry
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BufferPlexer.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\BufferPlexer.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BufferPlexer
-- Compiling architecture struct of BufferPlexer
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/R.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/R.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity REG8
-- Compiling architecture struct of REG8
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\ALU.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture struct of ALU
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/encoder.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/encoder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity encoder
-- Compiling architecture behav of encoder
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/HalfAdder.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/HalfAdder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity HalfAdder
-- Compiling architecture dataflow of HalfAdder
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/multiplexer.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/multiplexer.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux1
-- Compiling architecture behavioral of mux1
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/TB.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/TB.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity TB
-- Compiling architecture struct of TB
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MICOPOUT.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\MICOPOUT.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Loading package microoperations
-- Compiling entity MICOPOUT
-- Compiling architecture struct of MICOPOUT
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Z.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Z.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity Z
-- Compiling architecture behaviour of Z
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/CarryMux.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\CarryMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity carryMux
-- Compiling architecture behav of carryMux
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Fulladder.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Fulladder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity FullAdder
-- Compiling architecture structural of FullAdder
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/TwoOr.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/TwoOr.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity TwoOr
-- Compiling architecture dataflow of TwoOr
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/AddrReg.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/AddrReg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity AddrReg
-- Compiling architecture behav of AddrReg
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/paralleladder.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\paralleladder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity parelleladder
-- Compiling architecture BEHAVIOUR of parelleladder
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MicSeq.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MicSeq.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity micSeq
-- Compiling architecture struct of micSeq
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/INDREG.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/INDREG.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity INDREG16
-- Compiling architecture rtl of INDREG16
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/encoder.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\encoder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity encoder
-- Compiling architecture behav of encoder
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/INDREG.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/INDREG.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity INDREG8
-- Compiling architecture rtl of INDREG8
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/microoperations.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/microoperations.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling package microoperations
-- Compiling package body microoperations
-- Loading package microoperations
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/OverFlow.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/OverFlow.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity overflow
-- Compiling architecture behaviour of overflow
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/ALU.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/ALU.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity ALU
-- Compiling architecture struct of ALU
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/multiplexer2.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\multiplexer2.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux2
-- Compiling architecture behavioral of mux2
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/AddrMux.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity AddrMux
-- Compiling architecture behav of AddrMux
** Warning: [14] D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd(26): (vcom-1272) Length of expected is 6; length of actual is 7.
** Warning: [14] D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd(29): (vcom-1272) Length of expected is 6; length of actual is 7.
** Warning: [14] D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd(32): (vcom-1272) Length of expected is 6; length of actual is 7.
** Warning: [14] D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd(35): (vcom-1272) Length of expected is 6; length of actual is 7.
** Warning: [14] D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrMux.vhd(37): (vcom-1272) Length of expected is 6; length of actual is 7.
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/subroureg.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\subroureg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity subroureg
-- Compiling architecture behav of subroureg
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/microoperations.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\microoperations.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
** Warning: (vcom-6) -- Waiting for lock by "HarryM@DESKTOP-TB7NCE0, pid = 12424
". Lockfile is "D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Comp/_lock".
-- Compiling architecture theonethatsamixture of REG16
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling package microoperations
-- Compiling package body microoperations
-- Loading package microoperations
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/OPLUT.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/OPLUT.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity OPLUT
-- Compiling architecture struct of OPLUT
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ConditonMux.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\ConditonMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CondMux
-- Compiling architecture behav of CondMux
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/R.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/R.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity REG8
-- Compiling architecture struct of REG8
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/AddrMux.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/AddrMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity AddrMux
-- Compiling architecture behav of AddrMux
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/PC.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/PC.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity REG16
-- Compiling architecture theonethatsamixture of REG16
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/TR16.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/Registers/TR16.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity TR16
-- Compiling architecture rtl of TR16
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/OPLUT.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\OPLUT.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity OPLUT
-- Compiling architecture struct of OPLUT
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/subroureg.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/subroureg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity subroureg
-- Compiling architecture behav of subroureg
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/TwoOr.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/TwoOr.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity TwoOr
-- Compiling architecture dataflow of TwoOr
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MicMem.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/MicMem.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity MicMem
-- Compiling architecture behav of MicMem
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/ConditonMux.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/MicroSequencer/ConditonMux.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity CondMux
-- Compiling architecture behav of CondMux
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BTLOGIC.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\BTLOGIC.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BTLOGIC
-- Compiling architecture behavioural of BTLOGIC
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/myreg.vhd}} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/myreg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity myreg
-- Compiling architecture regbehav of myreg
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/BufferPlexer.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/BusBuffer/BufferPlexer.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity BufferPlexer
-- Compiling architecture struct of BufferPlexer
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/AdderGroup.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AdderGroup.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity AdderGroup
-- Compiling architecture struct of AdderGroup
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/TB.vhd} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\TB.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity TB
-- Compiling architecture struct of TB
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/paralleladder.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/paralleladder.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity parelleladder
-- Compiling architecture BEHAVIOUR of parelleladder
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/mux3.vhd} {1 {vcom -work work -2002 -explicit {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/ALU/mux3.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Compiling entity mux3
-- Compiling architecture behavioral of mux3
} {} {}} {D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/memory.vhd} {2 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\memory.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity sync_ram
-- Compiling architecture RTL of sync_ram
** Warning: D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\memory.vhd(66): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
} {} {}} {{D:/Documents/University/Year 2/Digital Design/Semester 2/RSCPU/AddrReg.vhd}} {1 {vcom -work work -2002 -explicit {D:\Documents\University\Year 2\Digital Design\Semester 2\RSCPU\AddrReg.vhd}
Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov 2 2012
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling entity AddrReg
-- Compiling architecture behav of AddrReg
} {} {}}