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Mostly because of the case of the integers where the desired size of the op would need to be inferred from the register, which would need additional verification code. |
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It would be great if it could be generated, so maybe there's a way around it? |
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Should I accept this for now and we look forward for some other way to add the rest? |
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I'll add these for now. |
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refers to #554 (labeled as "Good first issue")
I was thinking: the fact that C3 uses Oracle/Solaris syntax (the "{bwlq}" suffixes at the end of some instructions) makes it hard to mechanically add support for new ones, because the suffixes may or may not be valid for a given instruction... I am wondering, why not simply using "Intel/AMD mnemonics" as they are referred to in ASM Reference ? Then we could simply process the instructions.xml linked in the issue?