Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
To learn more and get started, visit https://tinytapeout.com.
- Add your Verilog files to the
srcfolder. - Edit the info.yaml and update information about your project, paying special attention to the
source_filesandtop_moduleproperties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool. - Edit docs/info.md and add a description of your project.
- Adapt the testbench to your design. See test/README.md for more information.
The GitHub action will automatically build the ASIC files using OpenLane.
- FAQ
- Digital design lessons
- Learn how semiconductors work
- Join the community
- Build your design locally
- Submit your design to the next shuttle.
- Edit this README and explain your design, how it works, and how to test it.
- Share your project on your social network of choice:
- LinkedIn #tinytapeout @TinyTapeout
- Mastodon #tinytapeout @matthewvenn
- X (formerly Twitter) #tinytapeout @tinytapeout
This project involves an attempt to design a CPU based on the HACK architecture introduced by Noam NISAN and Schimon SCHOKEN in their book The Elements of Computing Systems. The CPU itself consists of a 16-bit data bus, an SPI module for communication with memory, and another SPI module for sending debugging data. The main goal of the project is to test the capabilities and limitations of open-source tools used for microelectronic circuit design. Specifically, we've explored the OpenLane process to transform HDL files into synthesized outputs.
This project incorporates code and concepts from the nand2tetris project, and from the book "The Elements of Computing Systems" by Noam Nisan and Shimon Schocken. We are grateful for their workand contributions to the field of computer science education. For more information, please visit the nand2tetris website.
| Dantong LUO | Nour MHANNA | Charbel SAAD |
|---|---|---|
| dantong.luo@etu.emse.fr | nour.mhanna@etu.emse.fr | charbel.saad@etu.emse.fr |
| Alexendre MENU | Jean-Max DUTERTRE |
|---|---|
| alexendre.menu@emse.fr | dutertre@emse.fr |
As mentioned earlier, we utilized open-source software and programs. This section contains a list of the main tools we used during the project.
Icarus Verilog is designed to compile ALL Verilog HDL, as described in the IEEE-1364 standard. It effectively creates an executable that can be read by another program, 'vvp,' for test bench simulations.
Cocotb is a Python library that simplifies writing test benches to evaluate each module.
OpenLane is a process that combines a suite of programs and software with the goal of transforming HDL code into GDSII files that can be fabricated in a factory. The process also handles timing constraints and other physical constraints. Among these software tools, we find: Yosys, OpenROAD, ngspice, and Magic, etc.
This initiative aims to combine multiple circuits within a single chip. By doing so, the fabrication costs of chips can be shared among several small designers. The chip itself is divided into a series of tiles. Users choose the tile they want to interface with via a computer program running on a card connected to the chip.
As mentioned earlier, the CPU is based on the architecture presented in the book The Elements of Computing Systems. The main datapath is as follows:
Due to spatial constraints, we haven't been able to integrate memory inside the chip. Similarly, the number of external pins is insufficient to access data in parallel. Therefore, we needed a way to fetch data and instructions serially. We hence used the SPI protocol. Moreover, a debugging module, which also incorporates the SPI protocol, is present to facilitate CPU code design. The overall CPU schematic is as follows:
Testing the CPU is straightforward: the test bench executes a function that finds the fourth element of the Fibonacci sequence. It then tests the debugging module by sending and receiving the corresponding data. This Fibonacci function contains almost every type of instruction and thus, it is very efficient for testing the device.
For more information about the internal modules, we invite you to consult the documentation as well as the nand2tetris project that dives further into details about the CPU and its use.