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fix(rtl): fixed outputs for fpga synthesis Verilog Test Suite #6: Commit 4e151dc pushed by bsod2528
33s main
main
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chore: refactored inline docs for future reference Verilog Test Suite #5: Commit 52ebd78 pushed by bsod2528
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fix: removed unsused imports and stop actions error Verilog Test Suite #4: Commit 73fb673 pushed by bsod2528
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chore: updated changelog Verilog Test Suite #3: Commit 8ac9194 pushed by bsod2528
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fix(rtl): fixed fsm by adding a refetch (weird) state for cjmp Verilog Test Suite #2: Commit 82f862f pushed by bsod2528
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Merge pull request #1 from saint2706/main Verilog Test Suite #1: Commit c0e42da pushed by bsod2528
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