UPSTREAM PR #21168: ggml-cuda: ds_read_b128 for q4_0 and q4_1 mmq kernels#1319
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UPSTREAM PR #21168: ggml-cuda: ds_read_b128 for q4_0 and q4_1 mmq kernels#1319
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Current for loop generates ds_read_b32 instructions with hip compiler, the new solution generates ds_read_b128 instructions for the same operation, saving some LDS bandwidth. Tested on MI50 and RX6800XT, its faster on both.
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No meaningful performance changes were detected across 123908 analyzed functions in the following binaries: build.bin.llama-tts, build.bin.libllama.so, build.bin.llama-cvector-generator, build.bin.llama-bench, build.bin.libmtmd.so, build.bin.llama-gemma3-cli, build.bin.llama-gguf-split, build.bin.llama-llava-cli, build.bin.llama-minicpmv-cli, build.bin.llama-quantize, build.bin.llama-qwen2vl-cli, build.bin.llama-tokenize, build.bin.libggml-base.so, build.bin.libggml-cpu.so, build.bin.libggml.so. 🔎 Full breakdown: Loci Inspector |
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Source pull request: ggml-org/llama.cpp#21168
Overview
This pr is a LDS load optimization in mmq kernels for q4_0 and q4_1.
The activations loading loop has been restructured so that 8 * ds_read_b32 scalar operations are replaced by 2*vectorized ds_read_b128 by the HIP compiler. It ends up being about +10% in pp with the vega gpu, and a small speedup on the 6800xt.
This modification is guarded by GGML_USE_HIP flag. Since the code is duplicated in vec_dot_q4_0_q8_1_dp4a and vec_dot_q4_1_q8_1_dp4a kernels, it could be refactored in a single function that select the loading method.
Additional information
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