arch/mips: Add basic support for MIPS Creator CI20 board

arch/mips/Kconfig

@@ -30,6 +30,20 @@ config ARCH_CHIP_PIC32MZ
 	---help---
 		Microchip PIC32MZ (MIPS32)
 
+config ARCH_CHIP_JZ4780
+	bool "JZ4780"
+	select ARCH_MIPS32
+	select ARCH_HAVE_IRQPRIO
+	select ARCH_VECNOTIRQ
+	select ARCH_HAVE_RESET
+	select ARCH_HAVE_SERIAL_TERMIOS
+	select MIPS32_HAVE_DCACHE
+	select MIPS32_HAVE_ICACHE
+	select MIPS32_USE_WAIT_INSTRUCTION
+	select MIPS32_USE_SYSCALL_INSTRUCTION
+	---help---
+		Ingenic JZ4780 (MIPS32)
+
 config ARCH_CHIP_MIPS_CUSTOM
 	bool "Custom MIPS chip"
 	select ARCH_CHIP_CUSTOM
@@ -82,10 +96,12 @@ config ARCH_CHIP
 	string
 	default "pic32mx"	if ARCH_CHIP_PIC32MX
 	default "pic32mz"	if ARCH_CHIP_PIC32MZ
+	default "jz4780"	if ARCH_CHIP_JZ4780
 
 source "arch/mips/src/common/Kconfig"
 source "arch/mips/src/mips32/Kconfig"
 source "arch/mips/src/pic32mx/Kconfig"
 source "arch/mips/src/pic32mz/Kconfig"
+source "arch/mips/src/jz4780/Kconfig"
 
 endif

arch/mips/include/jz4780/chip.h

@@ -0,0 +1,157 @@
+/****************************************************************************
+ * arch/mips/include/jz4780/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H
+#define __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CKPCR               0xB0003040
+#define CKPCR_CK32CTL_RTCLK (3 << 1)
+
+#define JZINTC_BASE         0xB0001000
+
+#define ICMSR0              (JZINTC_BASE + 0x08)
+#define ICMCR0              (JZINTC_BASE + 0x0C)
+#define ICPR0               (JZINTC_BASE + 0x10)
+#define ICMSR1              (JZINTC_BASE + 0x28)
+#define ICMCR1              (JZINTC_BASE + 0x2C)
+#define ICPR1               (JZINTC_BASE + 0x30)
+
+#define JZTMR_BASE          0xB0002000
+
+#define WD_TDR              (JZTMR_BASE + 0x00) // u16: Watchdog Timer Data
+#define WD_TCER             (JZTMR_BASE + 0x04) // u8 : Watchdog Counter Enable
+#define WD_TCNT             (JZTMR_BASE + 0x08) // u16: Watchdog Timer Counter
+#define WD_TCSR             (JZTMR_BASE + 0x0C) // u16: Watchdog Timer Control
+
+#define TCSR_PRESCALE(x)    ((x) << 3)
+#define TCSR_DIV_16         2
+
+#define TCSR_EXT_EN         (1 << 2)
+#define TCSR_RTC_EN         (1 << 1)
+#define TCSR_PCK_EN         (1 << 0)
+
+#define TCER_TCEN           (1 << 0)
+
+#define OSTDR               (JZTMR_BASE + 0xe0)
+#define OSTCNTL             (JZTMR_BASE + 0xe4)
+#define OSTCNTH             (JZTMR_BASE + 0xe8)
+#define OSTCSR              (JZTMR_BASE + 0xec)
+
+#define TESR                (JZTMR_BASE + 0x14)
+
+#define TESR_OSTEN          (1 << 15)
+#define TESR_TCEN(n)        (1 << (n))
+
+#define TMSR                (JZTMR_BASE + 0x34)
+#define TMCR                (JZTMR_BASE + 0x38)
+#define TMCR_OSTMCL         (1 << 15)
+#define TMCR_FMCL5          (1 << 5)
+#define TMCR_FMCL(n)        (1 << (n))
+
+#define TFR                 (JZTMR_BASE + 0x20)
+
+#define TFCR                (JZTMR_BASE + 0x28)
+#define TFCR_OSTFCL         (1 << 15)
+#define TFCR_FFCL5          (1 << 5)
+#define TFCR_FFCL(n)        (1 << (n))
+
+#define TCNT(n)             (JZTMR_BASE + 0x48 + (n)*0x10)
+#define TCSR(n)             (JZTMR_BASE + 0x4C + (n)*0x10)
+#define TDFR(n)             (JZTMR_BASE + 0x40 + (n)*0x10)
+
+#define TICKS_PER_MS        (48000/16)
+
+#define CHIP_JZ4780         1
+#define CHIP_NPORTS         6  /* 6 ports (A-F) */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: jz_physregaddr
+ *
+ * Description:
+ *   Give the virtual address of a register, return the physical address of
+ *   the register
+ *
+ ****************************************************************************/
+
+uintptr_t jz_physregaddr(uintptr_t virtregaddr);
+
+/****************************************************************************
+ * Name: jz_physramaddr
+ *
+ * Description:
+ *   Give the virtual address of a RAM memory location, return the physical
+ *   address of that location.
+ *
+ ****************************************************************************/
+
+uintptr_t jz_physramaddr(uintptr_t vramaddr);
+
+/****************************************************************************
+ * Name: jz_virtramaddr
+ *
+ * Description:
+ *   Give the physical address of a RAM memory location, return the virtual
+ *   address of that location.
+ *
+ ****************************************************************************/
+
+uintptr_t jz_virtramaddr(uintptr_t physramaddr);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H */