Skip to content

xtensa/espressif: Update common-source integration for Xtensa devices #18614

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
tmedicci wants to merge 1 commit into
base: master
Choose a base branch
from
+11,308 −52,998
Open

xtensa/espressif: Update common-source integration for Xtensa devices #18614

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
The table of contents is too big for display.
Diff view
Diff view
  •  
  •  
  •  
2 changes: 1 addition & 1 deletion arch/risc-v/src/common/espressif/Make.defs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,7 @@ endif

ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309
ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif

ifndef ESP_HAL_3RDPARTY_URL
Expand Down
3 changes: 3 additions & 0 deletions arch/xtensa/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ config ARCH_CHIP_ESP32
select ARCH_HAVE_TESTSET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
Expand Down Expand Up @@ -56,6 +57,7 @@ config ARCH_CHIP_ESP32S2
select ARCH_HAVE_RESET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
Expand Down Expand Up @@ -92,6 +94,7 @@ config ARCH_CHIP_ESP32S3
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
Expand Down
37 changes: 27 additions & 10 deletions arch/xtensa/include/esp32/irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@

/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32_setup_irq needs.
* code calling esp_setup_irq needs.
*/

#define ESP32_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
Expand Down Expand Up @@ -190,24 +190,39 @@
*/

/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
* interrupts. These use negative source IDs for internal CPU interrupts.
*/

#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */

#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)

#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */

/* Legacy definitions for compatibility */

#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */

#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */

/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/

#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id)+XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)

#define ESP_IRQ2SOURCE(irq) ESP32_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32_PERIPH2IRQ(id)

/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */

Expand Down Expand Up @@ -299,7 +314,7 @@

#define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS

#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ

/* The PRO and APP CPU have different interrupts sources for the GPIO
* peripheral. Each CPU needs to allocate a separate interrupt and attach
Expand All @@ -325,6 +340,8 @@
# define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1)
# define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ)
# define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32_IRQ2PIN(i)
#else
# define ESP32_NIRQ_GPIO 0
#endif
Expand Down Expand Up @@ -477,7 +494,7 @@
* Inline functions
****************************************************************************/

#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
#ifdef CONFIG_SMP
static inline_function int esp32_irq_gpio(int cpu)
{
Expand Down
28 changes: 19 additions & 9 deletions arch/xtensa/include/esp32s2/irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -197,14 +197,19 @@
* interrupts
*/

#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */

#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)

#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */

/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
Expand All @@ -213,6 +218,9 @@
#define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)

#define ESP_IRQ2SOURCE(irq) ESP32S2_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S2_PERIPH2IRQ(id)

#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC_NMI)

Expand Down Expand Up @@ -304,12 +312,14 @@
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/

#ifdef CONFIG_ESP32S2_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 47
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S2_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S2_IRQ2PIN(i)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
Expand Down Expand Up @@ -360,7 +370,7 @@

/* Total number of interrupts */

#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)

/* Xtensa CPU Interrupts.
*
Expand Down
31 changes: 20 additions & 11 deletions arch/xtensa/include/esp32s3/irq.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@

/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32s3_setup_irq needs.
* code calling esp_setup_irq needs.
*/

#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
Expand Down Expand Up @@ -156,7 +156,6 @@
#define ESP32S3_PERIPH_AES 77
#define ESP32S3_PERIPH_SHA 78
#define ESP32S3_PERIPH_INT_FROM_CPU0 79

#define ESP32S3_PERIPH_INT_FROM_CPU1 80
#define ESP32S3_PERIPH_INT_FROM_CPU2 81
#define ESP32S3_PERIPH_INT_FROM_CPU3 82
Expand Down Expand Up @@ -201,14 +200,19 @@
* interrupts.
*/

#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */

#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)

#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */

/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
Expand All @@ -217,6 +221,9 @@
#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)

#define ESP_IRQ2SOURCE(irq) ESP32S3_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S3_PERIPH2IRQ(id)

#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
Expand Down Expand Up @@ -329,7 +336,7 @@

#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS

#ifdef CONFIG_ESP32S3_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ

/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
Expand All @@ -341,6 +348,8 @@
# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S3_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S3_IRQ2PIN(i)
#else
# define ESP32S3_NIRQ_GPIO 0
#endif
Expand Down Expand Up @@ -392,7 +401,7 @@

/* Total number of interrupts */

#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)

/* Xtensa CPU Interrupts.
*
Expand Down
Loading
Loading