arch/xtensa/esp32s3: Fix data transmission failure when buffer is in PSRAM#18350
arch/xtensa/esp32s3: Fix data transmission failure when buffer is in PSRAM#18350Y334275 wants to merge 1 commit intoapache:masterfrom
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PSRAM buffers require explicit cache management when used with DMA, as DMA accesses physical memory directly, bypassing the CPU cache. Before starting DMA transfer: - For an **OUTGOING** transfer (PSRAM -> Device): Call `cache_writeback_addr()` to flush dirty data from cache to PSRAM. - For an **INCOMING** transfer (Device -> PSRAM): Call `cache_invalidate_addr()` to invalidate cache lines, ensuring DMA can write to PSRAM. This ensures cache coherence and correct data transmission in burst mode. Signed-off-by: liu <liu334275@gmail.com>
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Don't merge yet, seems like there is another issue. |
I converted to Draft to avoid it being merged. Please let me know if you find out the new issue and I will proceed to review it ;) |
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According to ESP32-S3 Technical Reference Manual section 3.4.9 "Accessing External RAM":
This behavior can overwrite bytes after |
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Today I learned about those arrow drop-downs you used for the logs. Great idea, makes it much easier to scroll! Thank you :) |
Summary
PSRAM buffers require explicit cache management when used with DMA, as DMA accesses physical memory directly, bypassing the CPU cache.
Before starting DMA transfer:
cache_writeback_addr()to flush dirty data from cache to PSRAM.cache_invalidate_addr()to invalidate cache lines, ensuring DMA can write to PSRAM.This ensures cache coherence and correct data transmission in burst mode.
Impact
Testing
Environment
Test method
Added temporary debug logs in
esp32s3_spi_dma_exchangeto monitor transfer behavior.Here is the code:
Logs before fix
Logs after fix
Log comparison shows the fix is working:
0xf5 0x00and0xf6 0x00), indicating DMA failed to write data to the buffer (or read from it).defconfig shown below:
defconfig