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Feature vpto ci test#1

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Feature vpto ci test#1
and0d0 wants to merge 267 commits into
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feature-vpto-ci-test

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@and0d0 and0d0 commented May 27, 2026

测试b-mly->main ci整合

Zhendong404 and others added 30 commits May 25, 2026 11:13
    Introduce a three-pass pipeline that lowers PTO tile ops to vector-level
    implementations via TileLang DSL templates:

    - ExpandTileOp: invokes TileLang Python DSL to instantiate template
      functions and replaces tile ops with func.call. SpecKey covers all
      operands; tile_buf operands are passed through without bridging.
    - PTOInlineLibCall: extended to recognize tilelang instance functions via
      the  attribute set by the DSL frontend.
    - FoldTileBufIntrinsics: resolves pto.tile_buf_addr / tile_valid_rows /
      tile_valid_cols, including dynamic valid-shape via pto.bind_tile chain
      tracing.
    - MemrefToTileBuf: recovers tile_buf types from memref + bind_tile
      metadata after PlanMemory/InsertSync.
    - PTOViewToMemref: insert pto.bind_tile anchors for tile_buf function
      args so MemrefToTileBuf can recover them.

    Adds new PTO ops (tile_buf_addr/tile_valid_rows/tile_valid_cols),
    ptoas pipeline wiring, design docs, and unit tests.
mouliangyu and others added 20 commits May 25, 2026 11:14
* Rename VPTO MTE semantic ops

Input: existing VPTO memory-transfer semantic ops and tests using dma/cube/acc_store-style names.

Output: public semantic ops use mte_<src>_<dst> names, with ptr addrspace aliases for the new memory-space spelling.

Key steps: update ODS/parser/lowering/expand/ptr-normalize paths; migrate lit, VPTO, and TileLang test inputs; refresh VPTO/ISA docs and legacy raw-op wrapper mappings.

---------

Co-authored-by: mouliangyu <mouliangyu@huawei.com>
* Add OP for TMrgSort

* Add OP for TMrgSort | fix review

* Add constraints to tmov template for UB2UB ND2ND only

Add constraint function to restrict template_tmov_basic to only support:
- UB2UB: Both src and dst must be in Unified Buffer (memory_space="ub")
- ND2ND: Both tiles must have N-dimensional layout (s_layout=NONE_BOX)

Other scenarios (GM2UB, UB2GM, specialized layouts) require different
implementation paths and are explicitly rejected by this constraint.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

---------

Co-authored-by: caojian5 <caojian5@huawei.com>
Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
* Add HP (HIGH_PRECISION) support for TDiv

* Add HP for divs recip rowexpanddiv colexpanddiv

* [fix] Remove redundant else branch in HIGH_PRECISION mode since MLIR validation guarantees f16/f32 only

* [fix] Add missing HIGH_PRECISION test kernels for tdivs ST test

HP test cases were defined in cases.py but missing from implementation
files, causing FileNotFoundError when compare.py tried to read output.bin.

Added 12 HP kernels across three synced layers:
- tdivs.pto: HIGH_PRECISION kernels with precision_mode attribute
- main.cpp: kCases[] entries and launch wrapper declarations
- launch.cpp: Launch functions with correct IEEE 754 scalar values

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>

---------

Co-authored-by: caojian5 <caojian5@huawei.com>
Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>
@and0d0 and0d0 force-pushed the feature-vpto-ci-test branch from 16bbae4 to 0bf8b9a Compare May 27, 2026 02:46
@and0d0 and0d0 closed this May 27, 2026
@and0d0 and0d0 reopened this May 27, 2026
@and0d0 and0d0 closed this May 27, 2026
@and0d0 and0d0 reopened this May 27, 2026
@and0d0 and0d0 force-pushed the feature-vpto-ci-test branch from 0bf8b9a to 0429f76 Compare May 27, 2026 03:00
@and0d0 and0d0 closed this May 27, 2026
@and0d0 and0d0 reopened this May 27, 2026
@and0d0 and0d0 closed this May 27, 2026
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