library/axi_ad9361/xilinx: Fix frame delineation error check

[eemincetin]

The rx_error_r1 and rx_error_r2 checks were only using rx_frame_s (2 bits) instead of the concatenated {rx_frame_s, rx_frame} (4 bits) to properly validate frame alignment across consecutive clock cycles.

Signed-off-by: Emin Cetin eeminceetin@gmail.com

Warning - these changes have not been tested on the corresponding hardware / setup / boards!

PR Description

The rx_error_r1 and rx_error_r2 checks were only using rx_frame_s (2 bits)
instead of the concatenated {rx_frame_s, rx_frame} (4 bits) to properly
validate frame alignment across consecutive clock cycles.

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones