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Fix adrv9361 hold timing violations #1966

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Fix adrv9361 hold timing violations #1966

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71960b8
projects/scripts/route_design.tcl: initial commit
phlfm Dec 1, 2025
73a567f
adi_project_xilinx.tcl: added ADI_POST_ROUTE_POD_PRE_SCRIPT flag
phlfm Dec 1, 2025
835e012
projects/adrv9361z7035: route_design script added
phlfm Dec 1, 2025
5f65d98
projects/adrv9364: route_design script added
phlfm Dec 2, 2025
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2 changes: 2 additions & 0 deletions docs/user_guide/build_hdl.rst
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Expand Up @@ -596,6 +596,8 @@ when building a project:
operations. Default value is 8.
- **ADI_NO_BITSTREAM_COMPRESSION**: if set, disables compression of the final
bitstream file.
- **ADI_POST_ROUTE_POD_PRE_SCRIPT**: specifies the path to a Tcl script to be
executed before the phys_opt_design (POD) stage.
- **ADI_POST_ROUTE_SCRIPT**: specifies the path to a Tcl script to be executed
after the routing design step.
- **ADI_POWER_OPTIMIZATION**: if set to 1, enables power optimization during the
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3 changes: 2 additions & 1 deletion projects/adrv9361z7035/ccbob_cmos/system_project.tcl
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@@ -1,11 +1,12 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set ADI_POST_ROUTE_POD_PRE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/route_design.tcl]

adi_project_create adrv9361z7035_ccbob_cmos 0 {} "xc7z035ifbg676-2L"
adi_project_files adrv9361z7035_ccbob_cmos [list \
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3 changes: 2 additions & 1 deletion projects/adrv9361z7035/ccbob_lvds/system_project.tcl
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@@ -1,11 +1,12 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set ADI_POST_ROUTE_POD_PRE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/route_design.tcl]

adi_project_create adrv9361z7035_ccbob_lvds 0 {} "xc7z035ifbg676-2L"
adi_project_files adrv9361z7035_ccbob_lvds [list \
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3 changes: 2 additions & 1 deletion projects/adrv9361z7035/ccfmc_lvds/system_project.tcl
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@@ -1,11 +1,12 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set ADI_POST_ROUTE_POD_PRE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/route_design.tcl]

adi_project_create adrv9361z7035_ccfmc_lvds 0 {} "xc7z035ifbg676-2L"
adi_project_files adrv9361z7035_ccfmc_lvds [list \
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3 changes: 2 additions & 1 deletion projects/adrv9364z7020/ccbob_cmos/system_project.tcl
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@@ -1,11 +1,12 @@
###############################################################################
## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2016-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set ADI_POST_ROUTE_POD_PRE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/route_design.tcl]

adi_project_create adrv9364z7020_ccbob_cmos 0 {} "xc7z020clg400-1"
adi_project_files adrv9364z7020_ccbob_cmos [list \
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3 changes: 2 additions & 1 deletion projects/adrv9364z7020/ccbob_lvds/system_project.tcl
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@@ -1,11 +1,12 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
set ADI_POST_ROUTE_POD_PRE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/route_design.tcl]

adi_project_create adrv9364z7020_ccbob_lvds 0 {} "xc7z020clg400-1"
adi_project_files adrv9364z7020_ccbob_lvds [list \
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9 changes: 9 additions & 0 deletions projects/scripts/adi_project_xilinx.tcl
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Expand Up @@ -324,6 +324,7 @@ proc adi_project_create {project_name mode parameter_list device {board "not-app
# \param[project_files] - list of project files
#
proc adi_project_files {project_name project_files} {
global ADI_POST_ROUTE_POD_PRE_SCRIPT
global ADI_POST_ROUTE_SCRIPT

foreach pfile $project_files {
Expand All @@ -334,6 +335,9 @@ proc adi_project_files {project_name project_files} {
}
}

if {[info exists ADI_POST_ROUTE_POD_PRE_SCRIPT]} {
add_files -fileset utils_1 -norecurse ${ADI_POST_ROUTE_POD_PRE_SCRIPT}
}
if {[info exists ADI_POST_ROUTE_SCRIPT]} {
add_files -fileset utils_1 -norecurse ${ADI_POST_ROUTE_SCRIPT}
}
Expand All @@ -356,6 +360,7 @@ proc adi_project_run {project_name} {
global ADI_USE_OOC_SYNTHESIS
global ADI_MAX_OOC_JOBS
global ADI_GENERATE_BIN
global ADI_POST_ROUTE_POD_PRE_SCRIPT
global ADI_POST_ROUTE_SCRIPT

if {[info exists ::env(ADI_MAX_THREADS)]} {
Expand Down Expand Up @@ -395,6 +400,10 @@ proc adi_project_run {project_name} {

set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]

if {[info exists ADI_POST_ROUTE_POD_PRE_SCRIPT]} {
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.TCL.PRE [ get_files ${ADI_POST_ROUTE_POD_PRE_SCRIPT} -of [get_fileset utils_1] ] [get_runs impl_1]
}
if {[info exists ADI_POST_ROUTE_SCRIPT]} {
set_property STEPS.ROUTE_DESIGN.TCL.POST [ get_files ${ADI_POST_ROUTE_SCRIPT} -of [get_fileset utils_1] ] [get_runs impl_1]
}
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7 changes: 7 additions & 0 deletions projects/scripts/route_design.tcl
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@@ -0,0 +1,7 @@
# This script is used to fix some hold timing issues presented in more recent
# versions of vivado. This remedy was given by AMD employee through the xilinx
# forums.
# References:
# https://adaptivesupport.amd.com/s/question/0D5Pd00000pVOyuKAG/unexpected-hold-errors-when-moving-to-vivado-20251?language=en_US
# https://adaptivesupport.amd.com/s/question/0D5Pd0000153gqkKAA/persistent-hold-timing-violations-after-upgrading-to-vivado-2025x-physoptdesign-holdfix-ineffective?language=en_US
route_design