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tanmaykathpaliatanmaykathpalia
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HSD #16026967164: mmc: sdhci-cadence: Enable HS200/HS400 support and optimize timing parameters
Enable high-speed eMMC modes and improve Cadence V6 controller compatibility for Agilex5 platforms: Device tree changes: - Enable mmc-hs200-1_8v and mmc-hs400-1_8v support for eMMC - Increase max-frequency from 100MHz to 200MHz - Clear sdhci-caps-mask bit 13 to allow HS200/HS400 capabilities Driver improvements: - Add SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 for multiblock operations - Add SDHCI_QUIRK2_ACMD23_BROKEN to disable ACMD23 - Skip CMD13 status check after HS200 switch as Cadence IP times out instead of returning expected -EBADMSG error Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
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4 files changed

+39
-29
lines changed

4 files changed

+39
-29
lines changed

‎arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,17 +13,18 @@
1313
status = "okay";
1414
no-sd;
1515
no-sdio;
16-
no-1-8-v;
1716
disable-wp;
1817
non-removable;
1918
cap-mmc-highspeed;
19+
mmc-hs200-1_8v;
20+
mmc-hs400-1_8v;
2021

2122
bus-width = <8>;
2223
vmmc-supply = <&sd_emmc_power>;
2324
vqmmc-supply = <&emmc_io_1v8_reg>;
24-
max-frequency = <100000000>;
25+
max-frequency = <200000000>;
2526
sdhci-caps = <0x00000000 0x0000c800>;
26-
sdhci-caps-mask = <0x00002000 0x0000ff00>;
27+
sdhci-caps-mask = <0x00000000 0x0000ff00>;
2728
};
2829

2930
&nand {

‎drivers/mmc/core/mmc.c‎

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1503,16 +1503,23 @@ static int mmc_select_hs200(struct mmc_card *card)
15031503
* switch failed. If there really is a problem, we would expect
15041504
* tuning will fail and the result ends up the same.
15051505
*/
1506-
err = mmc_switch_status(card, false);
1506+
/*
1507+
* TODO: Cadence IP does not respond to CMD13 after switching to HS200,
1508+
* resulting in a timeout instead of the expected -EBADMSG failure.
1509+
* As a temporary workaround, mmc_switch_status() is skipped and tuning
1510+
* proceeds directly. Proper handling for CMD13 timeout or Cadence IP support
1511+
* should be implemented here.
1512+
*/
1513+
/* err = mmc_switch_status(card, false); */
15071514

15081515
/*
15091516
* mmc_select_timing() assumes timing has not changed if
15101517
* it is a switch error.
15111518
*/
1512-
if (err == -EBADMSG) {
1513-
mmc_set_clock(host, old_clock);
1514-
mmc_set_timing(host, old_timing);
1515-
}
1519+
// if (err == -EBADMSG) {
1520+
// mmc_set_clock(host, old_clock);
1521+
// mmc_set_timing(host, old_timing);
1522+
// }
15161523
}
15171524
err:
15181525
if (err) {

‎drivers/mmc/host/sdhci-cadence.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -427,8 +427,10 @@ static const struct sdhci_cdns_drv_data sdhci_cdns4_drv_data = {
427427
static const struct sdhci_cdns_drv_data sdhci_cdns6_agilex5_drv_data = {
428428
.pltfm_data = {
429429
.ops = &sdhci_cdns6_ops,
430+
.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
430431
.quirks2 = SDHCI_QUIRK2_40_BIT_DMA_MASK |
431-
SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
432+
SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
433+
SDHCI_QUIRK2_ACMD23_BROKEN,
432434
},
433435
};
434436

‎drivers/mmc/host/sdhci-cadence6.c‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
9696
{ "cdns,ctrl-hrs07-timing-delay-sd-sdr104", 0x000a0001 }, // SD UHS1 SDR104
9797
{ "cdns,ctrl-hrs07-timing-delay-sd-ddr50", 0x00090001 }, // SD UHS1 DDR50
9898
{ "cdns,ctrl-hrs07-timing-delay-mmc-ddr52", 0x00090001 }, // MMC DDR52
99-
{ "cdns,ctrl-hrs07-timing-delay-mmc-hs200", 0x00090000 }, // MMC HS200
99+
{ "cdns,ctrl-hrs07-timing-delay-mmc-hs200", 0x000a0001 }, // MMC HS200
100100
{ "cdns,ctrl-hrs07-timing-delay-mmc-hs400", 0x00090001 }, // MMC HS400
101101
{ "cdns,ctrl-hrs07-timing-delay-mmc-hs400es", 0x00090001 }, // MMC HS400ES
102102
},
@@ -126,7 +126,7 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
126126
{ "cdns,ctrl-hrs10-timing-delay-sd-sdr104", 0x00090000 },
127127
{ "cdns,ctrl-hrs10-timing-delay-sd-ddr50", 0x00020000 },
128128
{ "cdns,ctrl-hrs10-timing-delay-mmc-ddr52", 0x00020000 },
129-
{ "cdns,ctrl-hrs10-timing-delay-mmc-hs200", 0x00080000 },
129+
{ "cdns,ctrl-hrs10-timing-delay-mmc-hs200", 0x00090000 },
130130
{ "cdns,ctrl-hrs10-timing-delay-mmc-hs400", 0x00080000 },
131131
{ "cdns,ctrl-hrs10-timing-delay-mmc-hs400es", 0x00080000 },
132132
},
@@ -141,7 +141,7 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
141141
{ "cdns,ctrl-hrs16-timing-delay-sd-sdr104", 0x00000101 },
142142
{ "cdns,ctrl-hrs16-timing-delay-sd-ddr50", 0x11000000 },
143143
{ "cdns,ctrl-hrs16-timing-delay-mmc-ddr52", 0x11000001 },
144-
{ "cdns,ctrl-hrs16-timing-delay-mmc-hs200", 0x00007777 },
144+
{ "cdns,ctrl-hrs16-timing-delay-mmc-hs200", 0x00000101 },
145145
{ "cdns,ctrl-hrs16-timing-delay-mmc-hs400", 0x11000001 },
146146
{ "cdns,ctrl-hrs16-timing-delay-mmc-hs400es", 0x11000001 },
147147
},
@@ -162,18 +162,18 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
162162
},
163163
/* [5] ComboPHY: PHY Gate Loopback Control */
164164
{
165-
{ "cdns,phy-gate-lpbk_ctrl-delay-default", 0x81a40040 },
166-
{ "cdns,phy-gate-lpbk_ctrl-delay-mmc-hs", 0x81a40040 },
167-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-hs", 0x81a40040 },
168-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-sdr12", 0x81a40040 },
169-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-sdr25", 0x81a40040 },
170-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-sdr50", 0x80a40040 },
171-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-sdr104", 0x81a40040 },
172-
{ "cdns,phy-gate-lpbk_ctrl-delay-sd-ddr50", 0x80a40040 },
173-
{ "cdns,phy-gate-lpbk_ctrl-delay-mmc-ddr52", 0x81a40040 },
174-
{ "cdns,phy-gate-lpbk_ctrl-delay-mmc-hs200", 0x81a40040 },
175-
{ "cdns,phy-gate-lpbk_ctrl-delay-mmc-hs400", 0x81fc0040 },
176-
{ "cdns,phy-gate-lpbk_ctrl-delay-mmc-hs400es", 0x81fc0040 },
165+
{ "cdns,phy-gate-lpbk-ctrl-delay-default", 0x81a40040 },
166+
{ "cdns,phy-gate-lpbk-ctrl-delay-mmc-hs", 0x81a40040 },
167+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-hs", 0x81a40040 },
168+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-sdr12", 0x81a40040 },
169+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-sdr25", 0x81a40040 },
170+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-sdr50", 0x80a40040 },
171+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-sdr104", 0x81a40040 },
172+
{ "cdns,phy-gate-lpbk-ctrl-delay-sd-ddr50", 0x80a40040 },
173+
{ "cdns,phy-gate-lpbk-ctrl-delay-mmc-ddr52", 0x81a40040 },
174+
{ "cdns,phy-gate-lpbk-ctrl-delay-mmc-hs200", 0x81a40040 },
175+
{ "cdns,phy-gate-lpbk-ctrl-delay-mmc-hs400", 0x81fc0040 },
176+
{ "cdns,phy-gate-lpbk-ctrl-delay-mmc-hs400es", 0x81fc0040 },
177177
},
178178
/* [6] ComboPHY: PHY DLL Master Control */
179179
{
@@ -186,9 +186,9 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
186186
{ "cdns,phy-dll-master-ctrl-sd-sdr104", 0x00000004 },
187187
{ "cdns,phy-dll-master-ctrl-sd-ddr50", 0x00800000 },
188188
{ "cdns,phy-dll-master-ctrl-mmc-ddr52", 0x00800000 },
189-
{ "cdns,phy-dll-master-ctrl-mmc-hs200", 0x00204d00 },
190-
{ "cdns,phy-dll-master-ctrl-mmc-hs400", 0x00204d00 },
191-
{ "cdns,phy-dll-master-ctrl-mmc-hs400es", 0x00204d00 },
189+
{ "cdns,phy-dll-master-ctrl-mmc-hs200", 0x00000004 },
190+
{ "cdns,phy-dll-master-ctrl-mmc-hs400", 0x00000004 },
191+
{ "cdns,phy-dll-master-ctrl-mmc-hs400es", 0x00000004 },
192192
},
193193
/* [7] ComboPHY: PHY DLL Slave Control */
194194
{
@@ -201,7 +201,7 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
201201
{ "cdns,phy-dll-slave-ctrl-sd-sdr104", 0x004d4d00 },
202202
{ "cdns,phy-dll-slave-ctrl-sd-ddr50", 0x00000000 },
203203
{ "cdns,phy-dll-slave-ctrl-mmc-ddr52", 0x00000000 },
204-
{ "cdns,phy-dll-slave-ctrl-mmc-hs200", 0x004dc600 },
204+
{ "cdns,phy-dll-slave-ctrl-mmc-hs200", 0x004d4d00 },
205205
{ "cdns,phy-dll-slave-ctrl-mmc-hs400", 0x004d4b40 },
206206
{ "cdns,phy-dll-slave-ctrl-mmc-hs400es", 0x004d4b40 },
207207
},
@@ -216,7 +216,7 @@ static const struct sdhci_cdns6_ctrl_cfg reg_cfg[REG_CFG_MAX][MAX_TIMING_MODES]
216216
{ "cdns,phy-dq-timing-delay-sd-sdr104", 0x11000001 },
217217
{ "cdns,phy-dq-timing-delay-sd-ddr50", 0x38000001 },
218218
{ "cdns,phy-dq-timing-delay-mmc-ddr52", 0x10000001 },
219-
{ "cdns,phy-dq-timing-delay-mmc-hs200", 0x00000001 },
219+
{ "cdns,phy-dq-timing-delay-mmc-hs200", 0x10000001 },
220220
{ "cdns,phy-dq-timing-delay-mmc-hs400", 0x10000001 },
221221
{ "cdns,phy-dq-timing-delay-mmc-hs400es", 0x10000001 },
222222
}

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