HSD #14025230769: Update Agilex5 timers clock-freq to 100Mhz

100Mhz is the correct clock-freq for Agilex5 timers.

Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@altera.com>

Author: kuhanh

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi

@@ -1010,28 +1010,28 @@
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10c03000 0x100>;
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-			clock-freq = <400000000>;
+			clock-freq = <100000000>;
 		};
 
 		timer1: timer1@10c03100 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10c03100 0x100>;
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-			clock-freq = <400000000>;
+			clock-freq = <100000000>;
 		};
 
 		timer2: timer2@10d00000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10d00000 0x100>;
 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clock-freq = <400000000>;
+			clock-freq = <100000000>;
 		};
 
 		timer3: timer3@10d00100 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0x10d00100 0x100>;
 			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-			clock-freq = <400000000>;
+			clock-freq = <100000000>;
 		};
 
 		uart0: serial@10c02000 {