ViterbiDecoder

This is the repository for the course project for the course CS6230 offered at IIT Madras during the July-November 2025 Semester.

The project aims to develop a hardware accelerator for Viterbi Algorithm for decoding Hidden Markov Models (HMMs).

Directory Structure

.
├── hardware_model/             # Hardware implementation (Bluespec)
│   ├── defs/                   # Definitions and initialization data
│   │   ├── fpu.defines         # Hardware macros and constants
│   │   └── initmem.dat         # Initial memory contents
│   ├── Makefile                # Build/simulation Makefile for fpu
│   └── src/                    # Hardware source files
│       ├── fpu.bsv             # Base FPU module
│       ├── fpuPipelined.bsv    # Pipelined FPU implementation
│       ├── fpuTbFromFiles.bsv  # FPU testbench
│       ├── types.bsv           # Type definitions
│       ├── utils.bsv           # Utility Functions
│       ├── viterbi.bsv         # Viterbi decoder module
│       └── viterbi_tb.bsv      # Viterbi testbench
├── Makefile                    # Top-level project Makefile
├── README.md                    
├── software_model/             # Python reference implementation
│   ├── fpu/                    # FPU software model
│   │   ├── data_reader.py      # Reads input data for FPU simulations
│   │   └── main.py             # Entry point for FPU model
│   └── viterbi_decoder/        # Viterbi decoder software model
│       ├── data_reader.py      # Input reader for Viterbi decoder
│       ├── hmm_model.py        # HMM model implementation
│       └── main.py             # Entry point for Viterbi decoder
├── testlist.txt                # List of testcases for verification
└── verification/               # Scripts for generating/verifying test data
    ├── generator.py            # Test data generator
    └── main.py                 # Main verification script

Building

Generating verilog

make generate_verilog

Cleaning build directories

make deepclean

Running Standard Verification Tests

make run_all

Testing a case along with other tests

Assuming the testcase to be tested is called xyz, the files must be placed inside testcases/xyz/, and the test name must be appended to testlist.txt Each of the files must be suffixed by xyz, that is A_xyz.dat, B_xyz.dat and so on. The output simulated by the DUT is placed at testcases/xyz/Output_xyz.dat and the output simulated by the Python reference is placed in /testcases/xyz/out_xyz.dat. Finally, run:

make run_all

Testing a case individually

The same rules as above must be followed, except it is not necessary to add the file name to testlist.txt. If the test name is xyz, run:

make run_one_nogen TEST=xyz

Testing a randomly generated testcase

Run with suitable choices(following constraints) for N, M and NTEST

make tests N=10 M=10 NTEST=10

Stress testing

The special tests can be run multiple times(repeat_count) with generated inputs.

make run_all_repeated REPEAT=<repeat_count>

Individual Contribution

Abhinav I S

• Implemented the viterbi module and its testbench (viterbi.bsv, mkViterbi.bsv).

• Implemented software reference models for FPU and Viterbi Module. (software_model/fpu/, software_model/viterbi_decoder/)

Sanjeev Subrahmaniyan

• Implemented both baseline and pipelined FPU modules (fpu.bsv, fpuPipelined.bsv, fpuTbFromFiles.bsv)

• Implemented verification setup and specific testcases (testcases/, Makefile, verification/)

Maximum Clock Frequency Achieved

The synthesis for 32nm node was done using the liberty files from : saed32lvt ss0p75v25c.db. A maximum clock frequency of 317.4 MHz was achieved.