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1. IAC-Group-2/Team-2-RISCV-CPU IAC-Group-2/Team-2-RISCV-CPU Public

   EIE Y2 Instruction Architecture and Compilers coursework

   SystemVerilog

2. Lab1-Counter Lab1-Counter Public

   Forked from EIE2-IAC-Labs/Lab1-Counter

   IAC Labs

   C++

3. Lab2-SigGen Lab2-SigGen Public

   Forked from EIE2-IAC-Labs/Lab2-SigGen

   2nd Lab Instruction - Signal Generation and Capture

   C++

4. Lab3-FSM Lab3-FSM Public

   Forked from EIE2-IAC-Labs/Lab3-FSM

   Lab 3 is all about designing finite state machines

   C++

5. software_systems_assignment_1 software_systems_assignment_1 Public

   C

6. software_systems_assignment_2 software_systems_assignment_2 Public

   C