Martien.physreg liveranges by martien-de-jong · Pull Request #747 · Xilinx/llvm-aie

martien-de-jong · 2025-12-31T10:00:13Z

This is a POC of register allocation during postpipelining.

We add

RegDefUseTracker, taking care of virtualizing safe live ranges,
SchedulingInterpreter, computing register live ranges based on scheduled pipeline timing
PostRegAlloc, using the two to allocate the virtual registers after postpipelining.
Scarce range scheduling, a postpipelining scheduler heuristic avoiding overlap between liveranges that compete for a single register

Status:
It's aggressive enough to reach II=7 on gemm-bfp16-opt0, but sadly, the code it produces is not correct. I'm trying to find out what is causing my diff failure.

martien-de-jong · 2026-01-08T12:15:05Z

@@ -169,7 +169,7 @@ namespace llvm {
    /// Tracks the last instruction(s) in this region defining each virtual
    /// register. There may be multiple current definitions for a register with
    /// disjunct lanemasks.
-    VReg2SUnitMultiMap CurrentVRegDefs;
+    VReg2SUnitOperIdxMultiMap CurrentVRegDefs;


This was asymmetric between Uses and Defs. We need the operand index of the outstanding defs to compute operand latencies.

martien-de-jong · 2026-01-08T12:18:13Z

+
+  // Use TRI's regsOverlap which handles both physical and virtual registers,
+  // including subregisters and lane masks
+  return TRI->regsOverlap(SrcReg, DstReg);


I guess this was only needed transiently, but it looks really good.

nice they work on RegUnits

martien-de-jong · 2026-01-08T12:21:55Z

-        PostSWP->isPostPipelineCandidate(*TheBlock))
-      staticallyMaterializeMultiSlotInstructions(*TheBlock, HR);
+        PostSWP->isPostPipelineCandidate(*TheBlock)) {
+      staticallyMaterializeMultiSlotInstructions(*TheBlock, HR, MaterializeAll);


Would have been nice to be able to skip the scheduler before postpipelining. Sadly, the scheduler sometimes makes better decisions.

martien-de-jong · 2026-01-08T12:26:08Z

+    for (int T = 0; T < II; ++T) {
+      LaneBitmask Mask = LanesByOffset[T];
+      if (Mask.any()) {
+        // Show a simple indicator - could be enhanced to show actual lanes


Indeed. Full lanemasks are bulky though.

martien-de-jong · 2026-01-08T14:12:49Z

+static cl::opt<bool> TestRegDefUseTracker(
+    "aie-test-regdefuse-tracker", cl::Hidden, cl::init(false),
+    cl::desc("[AIE] TEST MODE: Run RegDefUseTracker analysis on all loops "
+             "(for testing only)"));


This is accommodating a dump for the early stages of live range analysis.

martien-de-jong · 2026-01-08T14:14:59Z

+
+void BlockState::restorePipelining() {
+  // Restore to the original allocation of the virtual registers
+  RegTracker->restoreOriginalPhysRegs();


These registers were used by the scheduler whose result we're going to use as a fallback.

martien-de-jong · 2026-01-13T14:15:51Z

+    BS.FixPoint.PipelinerMode = firstPipelinerMode();
+    if (BS.FixPoint.PipelinerMode != PostPipelinerMode::None) {
+      return SchedulingStage::Pipelining;
+    }


This looks a bit weird: we have been pipelining and are trying to restore to the first allowed pipelinermode for the next II. This should be invariant, so I don't think we can get None here. Perhaps assert.

martien-de-jong · 2026-01-13T14:21:24Z

+
+  // For virtual mode, re-analyze and virtualize
+  if (FixPoint.PipelinerMode == PostPipelinerMode::Virtual) {
+    // RegTracker might not exist if we have multiple regions


Someone missed that we can't do physical mode either if we have more than one region.
I would hope that RegTracker is always there for a SWP candidate.

andcarminati · 2026-02-11T08:18:04Z

+// - Merges aliasing register accesses into unified live ranges
+// - Filters out unsafe ranges (tied operands, live-in/out, implicit uses)
+// - Computes appropriate register classes for each live range
+// - Optionally replaces physical registers with virtual registers for testing


Check: are we going to use them to pipeline, apart of testing?

Yes, cline comment quirk.

andcarminati · 2026-02-11T08:20:09Z

+
+using namespace llvm;
+
+RegLiveRangeTracker::RegLiveRangeTracker(MachineBasicBlock &MBB)


Can we pass directly MF here? It is a bit confusing that we pass MBB but we don't use it "as is".

andcarminati · 2026-02-11T12:01:42Z

+
+void RegLiveRangeTracker::computeAliasClosure(MCRegister Reg,
+                                              DenseSet<MCRegister> &Out) const {
+  Out.insert(Reg);


Could we remove this by passing /*IncludeSelf*/=true in the first for?

Even better, we remove it in my current branch since it is suboptimal.

andcarminati · 2026-02-11T12:16:31Z

@@ -82,6 +83,13 @@ class InterBlockEdges {
 // handling.
 enum class BlockType { Regular, Loop, Epilogue };

+// PostPipelinerMode determines whether the postpipeliner operates on physical
+// registers or virtualizes them for better scheduling opportunities.
+enum class PostPipelinerMode { None, Physical, Virtual };


What Nome means?

None is just a default value. It can also be used as a sentinel to indicate end() when iterating through pipeliner modes.

mludevid · 2026-04-09T15:27:56Z

+    // Get the register class constraint for this operand
+    const TargetRegisterClass *OpRC =
+        MI->getRegClassConstraint(OpIdx, TII, TRI);


To resolve the bypass issue, we'd need to query if the MI uses itinerary-reg-pairs and get the reg class that was used to select the current itinerary. This would require a reverse look-up of those itinerary-reg-pairs, but that shouldn't be difficult to add to our tablegen backend. Correct?

…heduling

This is abstracting the live ranges to be used by PostRegAlloc

This module analyses live ranges of physical registers that can be safely reallocated in a basic block. It supplies facilities to rewrite to virtual registers and to restore the original allocation.

This module produces an EventSchedule from the instructions and their issue cycle. The event schedule contains the read and write events of the virtual registers occuring in the instructions ordered in the processor pipeline stage timeline. From the EventSchedule the modulo liveranges for a particular II can be constructed. These represent the lanes of each register that are live at a particular point.

This is a strategy that prioritizes scheduling of scarce ranges. Scarce ranges are live ranges that compete for one svailable register. The live ranges are virtualized, which means we have no serializing WAR deps. However, we need to be careful not to have more than one live, which means we want to finish the range before starting a new one. We try all legal permutations of these live ranges. For the current live range, we first prioritize all its ancestors, then the instructions in the range itself. Once we are finished with the range, we simulate the WAR dependences that are necessary to keep the next ranges non-overlapping

More aggressive check for liveout Slight logging changes. (perhaps to be split in separatecommit)

martien-de-jong requested review from F-Stuckmann, SagarMaheshwari99, abhinay-anubola, abnikant, andcarminati, katerynamuts, khallouh, konstantinschwarz, mludevid, niwinanto and stephenneuendorffer as code owners December 31, 2025 10:00

martien-de-jong marked this pull request as draft December 31, 2025 10:00

F-Stuckmann reviewed Jan 5, 2026

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Comment thread llvm/lib/Target/AIE/AIERegDefUseTracker.cpp Outdated

martien-de-jong force-pushed the martien.physreg-liveranges branch 2 times, most recently from cc8fca8 to 33264be Compare January 8, 2026 10:48

martien-de-jong marked this pull request as ready for review January 8, 2026 11:13

martien-de-jong commented Jan 8, 2026

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Comment thread llvm/lib/Target/AIE/AIEPostRegAlloc.cpp Outdated

martien-de-jong commented Jan 8, 2026

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Comment thread llvm/lib/Target/AIE/AIEPostRegAlloc.cpp Outdated

martien-de-jong commented Jan 8, 2026

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Comment thread llvm/lib/Target/AIE/AIEPostRegAlloc.cpp Outdated

martien-de-jong commented Jan 8, 2026

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martien-de-jong force-pushed the martien.physreg-liveranges branch from 7930abc to dcc908c Compare January 13, 2026 12:49

martien-de-jong commented Jan 13, 2026

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Comment thread llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

martien-de-jong commented Jan 13, 2026

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martien-de-jong force-pushed the martien.physreg-liveranges branch from dcc908c to 133f034 Compare January 30, 2026 12:03

andcarminati reviewed Feb 11, 2026

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martien-de-jong force-pushed the martien.physreg-liveranges branch from 699934a to 383d92b Compare February 19, 2026 17:07

martien-de-jong force-pushed the martien.physreg-liveranges branch from 383d92b to cf5d8e3 Compare April 8, 2026 16:19

mludevid reviewed Apr 9, 2026

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martien-de-jong force-pushed the martien.physreg-liveranges branch from cf5d8e3 to 2f5bea7 Compare April 13, 2026 15:54

Martien de Jong added 21 commits April 14, 2026 16:28

label edges consistenly

cbea80f

[AIE][POSTPIPELINER] Debug option to materialize the linear schedule

058e2e0

[AIEMachineScheduler] Track lane masks to accommodate VRegs in postsc…

83bf915

…heduling

[AIE] Add LivenessVector

6a7bd2c

This is abstracting the live ranges to be used by PostRegAlloc

[AIE] Add RegDefUseTracker

b45cb59

This module analyses live ranges of physical registers that can be safely reallocated in a basic block. It supplies facilities to rewrite to virtual registers and to restore the original allocation.

[AIE] Add PostRegAlloc

df210b0

[AIE] Add AIELiveRangeUtils

343363c

Virtual pipeliner mode integration

a7658d7

ref updates

6eb7220

[ScheduleDAGInstr] Add option not to skip registering full defs of VRegs

bb2a7c3

add tests

5e61cec

Add folding markers

9893cfe

Use non-live callee-changed for reallocation of virtualized regs

715f018

More aggressive check for liveout Slight logging changes. (perhaps to be split in separatecommit)

blind ref update

1ad91bf

add test for hnadling order of defs and ues

a107369

[AIE][INTERBLOCK] Don't overload BS.Fixpoint.II as pipelining indicator

3687a62

[AIE] Off-by-one error in dumpGraph

afd6b6d

RegDefUseTracker uses lanemasks and live-in to determine 'fully defined'

ff086b4

ref updates

b05c2bd

martien-de-jong force-pushed the martien.physreg-liveranges branch from 2f5bea7 to b05c2bd Compare April 14, 2026 14:32


		using namespace llvm;

		RegLiveRangeTracker::RegLiveRangeTracker(MachineBasicBlock &MBB)

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martien-de-jong commented Dec 31, 2025 •

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