NVC verilog support

tests/acceptance/test_artificial.py

@@ -135,7 +135,7 @@ def _test_artificial(self, args=None):
     def test_run_selected_tests_in_same_sim_test_bench_vhdl(self):
         self._test_run_selected_tests_in_same_sim_test_bench(self.artificial_run_vhdl)
 
-    @unittest.skipUnless(simulator_is("modelsim"), "Only modelsim supports verilog")
+    @unittest.skipUnless(simulator_is("modelsim", "nvc"), "Only modelsim and nvc support verilog")
     def test_run_selected_tests_in_same_sim_test_bench_verilog(self):
         self._test_run_selected_tests_in_same_sim_test_bench(self.artificial_run_verilog)
 
@@ -166,7 +166,7 @@ def _test_run_selected_tests_in_same_sim_test_bench(self, run_file):
             ],
         )
 
-    @unittest.skipUnless(simulator_is("modelsim"), "Only modelsim supports verilog")
+    @unittest.skipUnless(simulator_is("modelsim", "nvc"), "Only modelsim and nvc support verilog")
     def test_artificial_verilog(self):
         self.check(self.artificial_run_verilog, exit_code=1)
         check_report(

tests/acceptance/test_external_run_scripts.py

@@ -26,7 +26,7 @@ def simulator_supports_verilog():
     """
     Returns True if simulator supports Verilog
     """
-    return simulator_is("modelsim", "incisive")
+    return simulator_is("modelsim", "incisive", "nvc")
 
 
 # pylint: disable=too-many-public-methods
@@ -205,7 +205,7 @@ def test_vhdl_array_example_project(self):
         self.check(ROOT / "examples/vhdl/array/run.py")
 
     @mark.xfail(
-        not simulator_is("ghdl"),
+        not simulator_is("ghdl", "nvc"),
         reason="Only simulators with PSL functionality",
     )
     def test_vhdl_array_axis_vcs_example_project(self):

vunit/sim_if/nvc.py

@@ -191,6 +191,8 @@ def compile_source_file_command(self, source_file):
         """
         if source_file.is_vhdl:
             return self.compile_vhdl_file_command(source_file)
+        if source_file.is_any_verilog:
+            return self.compile_verilog_file_command(source_file)
 
         LOGGER.error("Unknown file type: %s", source_file.file_type)
         raise CompileError
@@ -214,7 +216,7 @@ def _std_str(vhdl_standard):
 
         raise ValueError(f"Invalid VHDL standard {vhdl_standard}")
 
-    def _get_command(self, std, worklib, workpath):
+    def _get_vhdl_command(self, std, worklib, workpath):
         """
         Get basic NVC command with global options
         """
@@ -233,7 +235,7 @@ def compile_vhdl_file_command(self, source_file):
         """
         Returns the command to compile a VHDL file
         """
-        cmd = self._get_command(
+        cmd = self._get_vhdl_command(
             source_file.get_vhdl_standard(), source_file.library.name, source_file.library.directory
         )
 
@@ -245,6 +247,32 @@ def compile_vhdl_file_command(self, source_file):
         cmd += [source_file.name]
         return cmd
 
+    def _get_verilog_command(self, worklib: str, workpath: str) -> list[str]:
+        cmd = [
+            str(Path(self._prefix) / self.executable),
+            f"--work={worklib}:{workpath!s}",
+        ]
+
+        for library in self._project.get_libraries():
+            cmd += [f"--map={library.name}:{library.directory}"]
+
+        return cmd
+
+    def compile_verilog_file_command(self, source_file):
+        """
+        Returns the command to compile a VHDL file
+        """
+
+        cmd = self._get_verilog_command(source_file.library.name, source_file.library.directory)
+
+        cmd += source_file.compile_options.get("nvc.global_flags", [])
+
+        cmd += ["-a"]
+        cmd += source_file.compile_options.get("nvc.a_flags", [])
+
+        cmd += [source_file.name]
+        return cmd
+
     def simulate(
         self, output_path, test_suite_name, config, elaborate_only
     ):  # pylint: disable=too-many-branches, disable=too-many-statements, disable=too-many-locals
@@ -258,7 +286,7 @@ def simulate(
             makedirs(script_path)
 
         libdir = self._project.get_library(config.library_name).directory
-        cmd = self._get_command(self._vhdl_standard, config.library_name, libdir)
+        cmd = self._get_vhdl_command(self._vhdl_standard, config.library_name, libdir)
 
         if self._gui:
             wave_file = script_path / (f"{config.entity_name}.{self._viewer_fmt or 'fst'}")