Automated FPGA Middleware for Power System Simulation

End-to-end Python automation pipeline that converts a discrete-time Simulink power system model (Emergency Diesel Generator) into HLS-ready C code, runs Vitis HLS synthesis on a Zynq-7000 FPGA, and compares hardware execution against the Simulink reference across five discrete step sizes (5, 25, 50, 75, 100 microseconds).

What it does

EmergencyDieselGenerator.slx
     |
     |  MATLAB engine + Embedded Coder (auto-generated C)
     v
Base C code
     |
     |  Clean for HLS (remove model.h, types, signal hooks)
     |  + custom HLS-compatible function for generator parameters
     v
HLS-ready C source
     |
     |  Per step size (5, 25, 50, 75, 100 us):
     |    - generate Vitis project + TCL + batch script
     |    - run vitis_hls.bat in synthesis mode
     v
Synthesizable RTL + IP per step size
     |
     |  Compare with Simulink 1 us reference (Va, Ic)
     v
Comparison tables + execution-time / error plots

Results

• 5.5x to 6x speedup over Simulink simulation
• Hardware latency of 7 cycles at 70 ns per simulation step on the xc7z020clg400-1 (Zynq-7000)
• FPGA mean error rates of 1e-11 to 1e-12 for voltage (Va), current (Ic), and mechanical power signals across the five step sizes
• V-shaped error curve, with optimal numerical accuracy at the 5 us and 100 us extremes

Hardware target

Parameter	Value
Device	Xilinx Zynq-7000
Part number	xc7z020clg400-1
HLS tool	Vitis HLS
RTL sim	Vivado

Files

File	Purpose
auto4.py	Main automation script (entire pipeline)
EmergencyDieselGenerator.slx	Simulink model of the diesel generator system

Configuration

Before running, edit the path constants near the top of auto4.py:

Variable	What to set
Output directory root	Where tables, generated code, and results land
Vitis HLS path	Full path to vitis_hls.bat
Vivado path	Full path to vivado.bat
Git binary directory	MSYS Git bin (needed for HLS toolchain on Windows)

Requirements

Tool	Use
Python 3.9+	Pipeline orchestration
MATLAB + Simulink + Embedded Coder	Model simulation, C code generation
Vitis HLS	C-to-RTL synthesis
Vivado	RTL behavioral simulation
Git (MSYS distribution on Windows)	Required by the HLS toolchain

Python deps: numpy, pandas, matplotlib.

Run

python auto4.py

The script:

1. Loads the Simulink reference signals (Va, Ic) from CSV
2. Computes mean relative error vs the reference at each step size
3. Calls MATLAB to generate C code from the Simulink model
4. Cleans the generated C for HLS compatibility
5. Creates one Vitis HLS project per step size and runs synthesis
6. Compiles a comparison table and writes summary plots

Output

CSV tables:

• table1_simulink_execution_time.csv
• table2_simulink_error.csv
• table3_fpga_results.csv
• simulink_execution_time.csv
• simulink_relative_errors.csv
• fpga_execution_time_and_accuracy.csv

Plots:

• simulink_execution_time.png
• simulink_error_analysis.png
• simulink_vs_fpga_execution_time.png
• simulink_vs_fpga_execution_time_horizontal.png

Per-step-size HLS projects:

• vitis_hls_proj_<step>us/ containing the synthesis report and IP
• generated_code/ and custom_hls/ with cleaned C and the custom generator-parameter helper function