Data bus w26

docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+it does not work
 
 ## How to test
 
-Explain how to use your project
+by inspection
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+ATP

info.yaml

@@ -1,9 +1,9 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  title:        "Interconnect Data Bus"      # Project title
+  author:       "1"      # Your name
+  discord:      "2"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Trasnfer data between modules"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -18,36 +18,42 @@ project:
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "project.v"
+    - "data_bus_ctrl.v"
+    - "data_bus_module_interface.v"
+    - "ack_bus_arbiter.v"
+    - "ack_bus_module_interface.v"
+    - "global_arbiter.v"
+    - "interconnect.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "ui_in0"   # corresponds to ui_in[0] in project.v
+  ui[1]: "ui_in1"   # ui_in[1]
+  ui[2]: "ui_in2"   # ui_in[2]
+  ui[3]: "ui_in3"   # ui_in[3]
+  ui[4]: "ui_in4"   # ui_in[4]
+  ui[5]: "ui_in5"   # ui_in[5]
+  ui[6]: "ui_in6"   # ui_in[6]
+  ui[7]: "ui_in7"   # ui_in[7]
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[0]: "uo_out0"  # corresponds to uo_out[0]
+  uo[1]: "uo_out1" 
+  uo[2]: "uo_out2"
+  uo[3]: "uo_out3"
+  uo[4]: "uo_out4"
+  uo[5]: "uo_out5"
+  uo[6]: "uo_out6"
+  uo[7]: "uo_out7"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
+  uio[0]: ""      # uio_out[0]
+  uio[1]: ""      # uio_out[1]
+  uio[2]: ""      # uio_out[2]
+  uio[3]: ""      # uio_out[3]
+  uio[4]: ""      # uio_out[4]
+  uio[5]: ""      # uio_out[5]
   uio[6]: ""
   uio[7]: ""
 

src/ack_bus_arbiter.v

@@ -32,28 +32,28 @@ always @(*) begin
     ack_valid_n = 1'b1;
     winner_source_id = 2'b11;   //CTRL has default ownship of the bus
 
-    if (ack_ready_to_ctrl == 1'b1) begin
+    if (ack_valid_from_ctrl == 1'b1) begin
       //CTRL module is asserting ack
       {ack_ready_to_ctrl, ack_ready_to_aes, ack_ready_to_sha, ack_ready_to_mem} = 4'b1000;
       ack_valid_n = 1'b0;
       winner_source_id = 2'b11;
     end
 
-    else if (ack_ready_to_aes == 1'b1) begin
+    else if (ack_valid_from_aes == 1'b1) begin
       //AES module is asserting ack
       {ack_ready_to_ctrl, ack_ready_to_aes, ack_ready_to_sha, ack_ready_to_mem} = 4'b0100;
       ack_valid_n = 1'b0;
       winner_source_id = 2'b10;
     end
 
-    else if (ack_ready_to_sha == 1'b1) begin
+    else if (ack_valid_from_sha == 1'b1) begin
       //SHA module is asserting ack
       {ack_ready_to_ctrl, ack_ready_to_aes, ack_ready_to_sha, ack_ready_to_mem} = 4'b0010;
       ack_valid_n = 1'b0;
       winner_source_id = 2'b01;
     end
 
-    else if (ack_ready_to_mem == 1'b1) begin
+    else if (ack_valid_from_mem == 1'b1) begin
       //MEM module is asserting ack
       {ack_ready_to_ctrl, ack_ready_to_aes, ack_ready_to_sha, ack_ready_to_mem} = 4'b0001;
       ack_valid_n = 1'b0;

src/ack_bus_module_interface.v

@@ -1,18 +1,18 @@
 module ack_bus_module_interface ( 
     input  wire        ACK_READY,
     output wire        ACK_READY_TO_MODULE,
-    input  wire        MODULE_SIDE_ACK_VAILD,
+    input  wire        MODULE_SIDE_ACK_VALID,
     output wire        ACK_VALID,
     input  wire [1:0]  MODULE_SIDE_MODULE_SOURCE_ID,
     output wire [1:0]  MODULE_SOURCE_ID
 );
 
 //READY
-//MODULE_SIDE_ACK_VALID->ACK_VAILD
+//MODULE_SIDE_ACK_VALID->ACK_VALID
 
-  assign ACK_READY=ACK_READY_TO_MODULE;
-  assign ACK_VAILD=MODULE_SIDE_ACK_VAILD;
-  assign MODULE_SOURCE_ID=MODULE_SIDE_MODULE_SOURCE_ID;
+  assign ACK_READY_TO_MODULE = ACK_READY;
+  assign ACK_VALID = MODULE_SIDE_ACK_VALID;
+  assign MODULE_SOURCE_ID = MODULE_SIDE_MODULE_SOURCE_ID;
 
 //This is an example of what the interfacing should look like, realistically the central ack_bus module will take care of all the interfacing
 //We can refer back to this in the future
@@ -30,4 +30,4 @@ How to use:
 ACK Bus:
 
 The Ack bus receive the signals and
-*/
+*/