queues and some reg shaving. pr to manage this merge as I don't want everything#3
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ryan-uwaterloo wants to merge 6 commits into
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queues and some reg shaving. pr to manage this merge as I don't want everything#3ryan-uwaterloo wants to merge 6 commits into
ryan-uwaterloo wants to merge 6 commits into
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- Delete sha_top.v, sha_fsm.v, scoreboard.v (SHA never implemented) - Remove all SHA wiring from control_top, bus_arbiter, interconnect, global_arbiter, deserializer, req_queue, comp_queue, project.v - mem_txn_fsm: remove 13 flash init states (power-on, chip erase, QE bit SR2 write); assumes flash pre-configured for QSPI. Counter shrunk 27->16 bit. qed initialized to 1. - Register width tightening: AES.v byte_cnt 6->5b, aes_core_rs key_idx 6->5b, mem_command_port state 4->3b / counter 8->5b / opcode 8->6b - Queue depth: req_queue and comp_queue QDEPTH 4->2 - Add synth/ scripts for local Yosys area estimation - Yosys stat: 8768 cells, 1533 FFs (was ~6x2 worth of logic)
- Makefile: remove scoreboard.v, sha_top.v, sha_fsm.v from PROJECT_SOURCES - reset_test: remove all flash init sequence assertions (WREN/SW RST/chip erase/RDSR2/WRSR2 no longer happen); now just verifies IO2/IO3 output enables are set and CS stays de-asserted for 200 cycles after reset - aes_encryption_test: add reset_dut() call (was commented out via reset_test which no longer applies); WIP poll expectations unchanged since mem_txn_fsm still WIP-polls before every flash operation
- aes_core_rs.v: key_idx reset literal 6'd0 -> 5'd0 (reg is 5-bit)
- AES.v: header_byte reset literal 5'd0 -> 6'd0 (reg is 6-bit)
- mem_command_port.v: explicit zero-extend internal_opcode to 8 bits
in PASS_CMD_WAIT_READY ({2'b0, internal_opcode})
- mem_txn_fsm.v: remove unused 'none' localparam
- reset_test: remove uio_oe assertion; uio_oe is 0 during idle (SPI
controller only drives IO pins during an active transaction)
Reverts the flash init removal: SW RST, WIP poll, global unlock, chip erase, RDSR2/WRSR2 (QE bit enable) are all back. Counter restored to 27-bit, qed initialises to 0. reset_test restored to verify full init sequence. Area reduction from this file is forfeited.
The hardware starts the flash init sequence autonomously after reset. aes_encryption_test was calling reset_dut() then immediately sending a CPU opcode while the DUT was busy with init — causing a deadlock. Fix: extract flash_init(dut) coroutine that drives the testbench flash side through the full init sequence (WREN/SW RST/WIP poll/chip erase/ RDSR2/WRSR2/WIP poll) with assertions. Both reset_test and aes_encryption_test now call reset_dut() then flash_init() before proceeding.
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do not merge this - for visualization purposes |
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