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JefferyLim wants to merge 7 commits into from
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Fix #2

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45d5bb1
Fixing the OS4C repository
JefferyLim Apr 30, 2026
c814208
Remove extra whitespace in mqnic_core_pcie.v
JefferyLim Apr 30, 2026
410dd66
Enable RS FEC for QSFP CMAC instances
JefferyLim Apr 30, 2026
6d1c688
Remove debug logging for queue counts
JefferyLim Apr 30, 2026
97589fa
Removing redundant directory
JefferyLim Apr 30, 2026
e1c6720
Fixing cqm_aruser in cpl_queue
JefferyLim Apr 30, 2026
3eee593
Remove IRQ index logging in mqnic_irq.c
JefferyLim Apr 30, 2026
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1 change: 1 addition & 0 deletions LICENSE
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@@ -1,3 +1,4 @@
Copyright (c) 2026, Jeffery Lim
Copyright (c) 2024, Scott Smith
Copyright (c) 2019-2023, The Regents of the University of California.
All rights reserved.
Expand Down
5 changes: 2 additions & 3 deletions fpga/common/rtl/mqnic_core_pcie.v
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Expand Up @@ -1291,13 +1291,12 @@ wire [FUNCTION_ID_WIDTH-1:0] axil_msix_write_function_id;

// Scott
resource_translator #(
.TOTAL_RESOURCES(2**(FUNCTION_ID_WIDTH + IRQ_INDEX_WIDTH)),
.TOTAL_RESOURCES(2**(FUNCTION_ID_WIDTH + IRQ_INDEX_WIDTH + 1)),
.FUNCTION_ID_WIDTH(FUNCTION_ID_WIDTH),
.RESOURCE_BIT_WIDTH(32'd2), // 4-bits per cpl queue
.RESOURCE_BIT_WIDTH(32'd3), // 3-bits per msi-x
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH)
)
pcie_msix_resource_translator (

.input_write_address(axil_msix_awaddr),
.input_write_function_id(axil_msix_awuser),

Expand Down
21 changes: 14 additions & 7 deletions fpga/common/rtl/mqnic_interface.v
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Expand Up @@ -1031,6 +1031,10 @@ wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data;
wire ctrl_reg_rd_wait;
wire ctrl_reg_rd_ack;

wire [8-1:0] ctrl_reg_wr_user;
wire [8-1:0] ctrl_reg_rd_user;


axil_reg_if #(
.DATA_WIDTH(REG_DATA_WIDTH),
.ADDR_WIDTH(REG_ADDR_WIDTH),
Expand All @@ -1045,7 +1049,7 @@ axil_reg_if_inst (
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_ctrl_awaddr),
// .s_axil_awuser(axil_ctrl_awuser), // Scott
.s_axil_awuser(axil_ctrl_awuser), // Scott
.s_axil_awprot(axil_ctrl_awprot),
.s_axil_awvalid(axil_ctrl_awvalid),
.s_axil_awready(axil_ctrl_awready),
Expand All @@ -1057,7 +1061,7 @@ axil_reg_if_inst (
.s_axil_bvalid(axil_ctrl_bvalid),
.s_axil_bready(axil_ctrl_bready),
.s_axil_araddr(axil_ctrl_araddr),
// .s_axil_aruser(axil_ctrl_aruser), // Scott
.s_axil_aruser(axil_ctrl_aruser), // Scott
.s_axil_arprot(axil_ctrl_arprot),
.s_axil_arvalid(axil_ctrl_arvalid),
.s_axil_arready(axil_ctrl_arready),
Expand All @@ -1072,10 +1076,12 @@ axil_reg_if_inst (
.reg_wr_addr(ctrl_reg_wr_addr),
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_user(ctrl_reg_wr_user),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(ctrl_reg_wr_wait),
.reg_wr_ack(ctrl_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_user(ctrl_reg_rd_user),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(ctrl_reg_rd_data),
.reg_rd_wait(ctrl_reg_rd_wait),
Expand Down Expand Up @@ -1181,6 +1187,7 @@ always @(posedge clk) begin
end
RBB+8'h10: ctrl_reg_rd_data_reg <= PORTS; // IF ctrl: Port count
RBB+8'h14: ctrl_reg_rd_data_reg <= SCHEDULERS; // IF ctrl: Scheduler count
RBB+8'h18: ctrl_reg_rd_data_reg <= ctrl_reg_rd_user; // IF ctrl: Assigned MAC/VF ID
RBB+8'h20: ctrl_reg_rd_data_reg <= MAX_TX_SIZE; // IF ctrl: Max TX MTU
RBB+8'h24: ctrl_reg_rd_data_reg <= MAX_RX_SIZE; // IF ctrl: Max RX MTU
RBB+8'h28: ctrl_reg_rd_data_reg <= tx_mtu_reg; // IF ctrl: TX MTU
Expand Down Expand Up @@ -1722,7 +1729,7 @@ cpl_queue_resource_translator_inst(
.input_write_function_id(axil_cqm_awuser),

.input_read_address(axil_cqm_araddr),
.input_read_function_id(axil_eqm_aruser),
.input_read_function_id(axil_cqm_aruser),

.output_read_address(axil_cqm_araddr_translated),
.output_write_address(axil_cqm_awaddr_translated),
Expand Down Expand Up @@ -2071,8 +2078,8 @@ tx_qm_inst (
/*
* AXI-Lite slave interface
*/
.s_axil_awaddr(axil_tx_qm_awaddr),
.s_axil_awuser(axil_tx_qm_awuser), // Scott
.s_axil_awaddr(axil_tx_qm_awaddr_translated),
.s_axil_awuser(axil_tx_qm_write_function_id), // Scott
.s_axil_awprot(axil_tx_qm_awprot),
.s_axil_awvalid(axil_tx_qm_awvalid),
.s_axil_awready(axil_tx_qm_awready),
Expand All @@ -2083,8 +2090,8 @@ tx_qm_inst (
.s_axil_bresp(axil_tx_qm_bresp),
.s_axil_bvalid(axil_tx_qm_bvalid),
.s_axil_bready(axil_tx_qm_bready),
.s_axil_araddr(axil_tx_qm_araddr),
.s_axil_aruser(axil_tx_qm_aruser), // Scott
.s_axil_araddr(axil_tx_qm_araddr_translated),
.s_axil_aruser(axil_tx_qm_read_function_id), // Scott
.s_axil_arprot(axil_tx_qm_arprot),
.s_axil_arvalid(axil_tx_qm_arvalid),
.s_axil_arready(axil_tx_qm_arready),
Expand Down
2 changes: 1 addition & 1 deletion fpga/common/rtl/queue_manager.v
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Expand Up @@ -519,7 +519,7 @@ always @* begin
queue_ram_be[8] = 1'b1;
end else begin
queue_ram_be[8] = 1'b1;
queue_ram_write_data[71:64] = axil_reg_pipeline_function_id_reg[PIPELINE-1]
queue_ram_write_data[71:64] = axil_reg_pipeline_function_id_reg[PIPELINE-1];
end
end
32'h8002zzzz: begin
Expand Down
14 changes: 14 additions & 0 deletions fpga/lib/axi/rtl/axil_reg_if.v
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Expand Up @@ -39,8 +39,12 @@ module axil_reg_if #
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Width of user bus in bits
parameter USER_WIDTH = 8,

// Timeout delay (cycles)
parameter TIMEOUT = 4

)
(
input wire clk,
Expand All @@ -52,6 +56,7 @@ module axil_reg_if #
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
input wire [USER_WIDTH-1:0] s_axil_awuser,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
Expand All @@ -62,6 +67,7 @@ module axil_reg_if #
input wire s_axil_bready,
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [2:0] s_axil_arprot,
input wire [USER_WIDTH-1:0] s_axil_aruser,
input wire s_axil_arvalid,
output wire s_axil_arready,
output wire [DATA_WIDTH-1:0] s_axil_rdata,
Expand All @@ -74,11 +80,13 @@ module axil_reg_if #
*/
output wire [ADDR_WIDTH-1:0] reg_wr_addr,
output wire [DATA_WIDTH-1:0] reg_wr_data,
output wire [USER_WIDTH-1:0] reg_wr_user,
output wire [STRB_WIDTH-1:0] reg_wr_strb,
output wire reg_wr_en,
input wire reg_wr_wait,
input wire reg_wr_ack,
output wire [ADDR_WIDTH-1:0] reg_rd_addr,
output wire [USER_WIDTH-1:0] reg_rd_user,
output wire reg_rd_en,
input wire [DATA_WIDTH-1:0] reg_rd_data,
input wire reg_rd_wait,
Expand All @@ -89,6 +97,7 @@ axil_reg_if_wr #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.USER_WIDTH(USER_WIDTH),
.TIMEOUT(TIMEOUT)
)
axil_reg_if_wr_inst (
Expand All @@ -100,6 +109,7 @@ axil_reg_if_wr_inst (
*/
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awuser(s_axil_awuser),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
Expand All @@ -115,6 +125,7 @@ axil_reg_if_wr_inst (
*/
.reg_wr_addr(reg_wr_addr),
.reg_wr_data(reg_wr_data),
.reg_wr_user(reg_wr_user),
.reg_wr_strb(reg_wr_strb),
.reg_wr_en(reg_wr_en),
.reg_wr_wait(reg_wr_wait),
Expand All @@ -125,6 +136,7 @@ axil_reg_if_rd #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.USER_WIDTH(USER_WIDTH),
.TIMEOUT(TIMEOUT)
)
axil_reg_if_rd_inst (
Expand All @@ -136,6 +148,7 @@ axil_reg_if_rd_inst (
*/
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_aruser(s_axil_aruser),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
Expand All @@ -148,6 +161,7 @@ axil_reg_if_rd_inst (
*/
.reg_rd_addr(reg_rd_addr),
.reg_rd_en(reg_rd_en),
.reg_rd_user(reg_rd_user),
.reg_rd_data(reg_rd_data),
.reg_rd_wait(reg_rd_wait),
.reg_rd_ack(reg_rd_ack)
Expand Down
13 changes: 13 additions & 0 deletions fpga/lib/axi/rtl/axil_reg_if_rd.v
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Expand Up @@ -39,6 +39,8 @@ module axil_reg_if_rd #
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Width of user bus in bits
parameter USER_WIDTH = 8,
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
Expand All @@ -50,6 +52,7 @@ module axil_reg_if_rd #
* AXI-Lite slave interface
*/
input wire [ADDR_WIDTH-1:0] s_axil_araddr,
input wire [USER_WIDTH-1:0] s_axil_aruser,
input wire [2:0] s_axil_arprot,
input wire s_axil_arvalid,
output wire s_axil_arready,
Expand All @@ -63,6 +66,7 @@ module axil_reg_if_rd #
*/
output wire [ADDR_WIDTH-1:0] reg_rd_addr,
output wire reg_rd_en,
output wire [USER_WIDTH-1:0] reg_rd_user,
input wire [DATA_WIDTH-1:0] reg_rd_data,
input wire reg_rd_wait,
input wire reg_rd_ack
Expand All @@ -77,6 +81,8 @@ reg s_axil_arvalid_reg = 1'b0, s_axil_arvalid_next;
reg [DATA_WIDTH-1:0] s_axil_rdata_reg = {DATA_WIDTH{1'b0}}, s_axil_rdata_next;
reg s_axil_rvalid_reg = 1'b0, s_axil_rvalid_next;

reg [USER_WIDTH-1:0] s_axil_aruser_reg = {USER_WIDTH{1'b0}}, s_axil_aruser_next;

reg reg_rd_en_reg = 1'b0, reg_rd_en_next;

assign s_axil_arready = !s_axil_arvalid_reg;
Expand All @@ -87,6 +93,8 @@ assign s_axil_rvalid = s_axil_rvalid_reg;
assign reg_rd_addr = s_axil_araddr_reg;
assign reg_rd_en = reg_rd_en_reg;

assign reg_rd_user = s_axil_aruser_reg;

always @* begin
timeout_count_next = timeout_count_reg;

Expand All @@ -95,6 +103,8 @@ always @* begin
s_axil_rdata_next = s_axil_rdata_reg;
s_axil_rvalid_next = s_axil_rvalid_reg && !s_axil_rready;

s_axil_aruser_next = s_axil_aruser_reg;

if (reg_rd_en_reg && (reg_rd_ack || timeout_count_reg == 0)) begin
s_axil_arvalid_next = 1'b0;
s_axil_rdata_next = reg_rd_data;
Expand All @@ -104,6 +114,7 @@ always @* begin
if (!s_axil_arvalid_reg) begin
s_axil_araddr_next = s_axil_araddr;
s_axil_arvalid_next = s_axil_arvalid;
s_axil_aruser_next = s_axil_aruser;
timeout_count_next = TIMEOUT-1;
end

Expand All @@ -122,6 +133,8 @@ always @(posedge clk) begin
s_axil_rdata_reg <= s_axil_rdata_next;
s_axil_rvalid_reg <= s_axil_rvalid_next;

s_axil_aruser_reg <= s_axil_aruser_next;

reg_rd_en_reg <= reg_rd_en_next;

if (rst) begin
Expand Down
12 changes: 12 additions & 0 deletions fpga/lib/axi/rtl/axil_reg_if_wr.v
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Expand Up @@ -39,6 +39,8 @@ module axil_reg_if_wr #
parameter ADDR_WIDTH = 32,
// Width of wstrb (width of data bus in words)
parameter STRB_WIDTH = (DATA_WIDTH/8),
// Width of user bus in bits
parameter USER_WIDTH = 8,
// Timeout delay (cycles)
parameter TIMEOUT = 4
)
Expand All @@ -52,6 +54,7 @@ module axil_reg_if_wr #
input wire [ADDR_WIDTH-1:0] s_axil_awaddr,
input wire [2:0] s_axil_awprot,
input wire s_axil_awvalid,
input wire [USER_WIDTH-1:0] s_axil_awuser,
output wire s_axil_awready,
input wire [DATA_WIDTH-1:0] s_axil_wdata,
input wire [STRB_WIDTH-1:0] s_axil_wstrb,
Expand All @@ -68,6 +71,7 @@ module axil_reg_if_wr #
output wire [DATA_WIDTH-1:0] reg_wr_data,
output wire [STRB_WIDTH-1:0] reg_wr_strb,
output wire reg_wr_en,
output wire [USER_WIDTH-1:0] reg_wr_user,
input wire reg_wr_wait,
input wire reg_wr_ack
);
Expand All @@ -83,6 +87,9 @@ reg [STRB_WIDTH-1:0] s_axil_wstrb_reg = {STRB_WIDTH{1'b0}}, s_axil_wstrb_next;
reg s_axil_wvalid_reg = 1'b0, s_axil_wvalid_next;
reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;


reg [USER_WIDTH-1:0] s_axil_awuser_reg = {USER_WIDTH{1'b0}}, s_axil_awuser_next;

reg reg_wr_en_reg = 1'b0, reg_wr_en_next;

assign s_axil_awready = !s_axil_awvalid_reg;
Expand All @@ -95,11 +102,14 @@ assign reg_wr_data = s_axil_wdata_reg;
assign reg_wr_strb = s_axil_wstrb_reg;
assign reg_wr_en = reg_wr_en_reg;

assign reg_wr_user = s_axil_awuser_reg;

always @* begin
timeout_count_next = timeout_count_reg;

s_axil_awaddr_next = s_axil_awaddr_reg;
s_axil_awvalid_next = s_axil_awvalid_reg;
s_axil_awuser_next = s_axil_awuser_reg;
s_axil_wdata_next = s_axil_wdata_reg;
s_axil_wstrb_next = s_axil_wstrb_reg;
s_axil_wvalid_next = s_axil_wvalid_reg;
Expand All @@ -114,6 +124,7 @@ always @* begin
if (!s_axil_awvalid_reg) begin
s_axil_awaddr_next = s_axil_awaddr;
s_axil_awvalid_next = s_axil_awvalid;
s_axil_awuser_next = s_axil_awuser;
timeout_count_next = TIMEOUT-1;
end

Expand All @@ -136,6 +147,7 @@ always @(posedge clk) begin
s_axil_awaddr_reg <= s_axil_awaddr_next;
s_axil_awvalid_reg <= s_axil_awvalid_next;
s_axil_wdata_reg <= s_axil_wdata_next;
s_axil_awuser_reg <= s_axil_awuser_next;
s_axil_wstrb_reg <= s_axil_wstrb_next;
s_axil_wvalid_reg <= s_axil_wvalid_next;
s_axil_bvalid_reg <= s_axil_bvalid_next;
Expand Down
6 changes: 3 additions & 3 deletions fpga/lib/pcie/rtl/pcie_msix.v
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Expand Up @@ -104,7 +104,7 @@ module pcie_msix #

parameter TBL_ADDR_WIDTH = IRQ_INDEX_WIDTH+1;
parameter NUM_TABLE_ENTRIES = 2**TBL_ADDR_WIDTH; // Scott
parameter NUM_ENTRIES_PER_FUNC = NUM_TABLE_ENTRIES / FUNCTION_ID_WIDTH;
parameter NUM_ENTRIES_PER_FUNC = NUM_TABLE_ENTRIES / 2**FUNCTION_ID_WIDTH;
parameter CLOG_NUM_ENTRIES_PER_FUNC = $clog2(NUM_ENTRIES_PER_FUNC);

parameter PBA_ADDR_WIDTH = IRQ_INDEX_WIDTH > 6 ? IRQ_INDEX_WIDTH-6 : 0;
Expand Down Expand Up @@ -303,9 +303,9 @@ always @* begin
tlp_hdr[109:108] = 2'b00; // attr
tlp_hdr[107:106] = 3'b000; // AT
tlp_hdr[105:96] = 10'd1; // length
// DW 1
// DW
//$display("Scott irq_index_reg = %b", irq_index_reg);
func_id[7:0] = irq_index_reg >> CLOG_NUM_ENTRIES_PER_FUNC;
func_id[7:0] = irq_index_reg >> (CLOG_NUM_ENTRIES_PER_FUNC-1);
tlp_hdr[95:80] = {8'b0, func_id}; // requester ID
//$display("Scott tlp_hdr = %b ", tlp_hdr[95:80]);
tlp_hdr[79:72] = 8'd0; // tag
Expand Down
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