Fix sampling to be in the exact middle of start signal

Author: TimRudy

Uart8Receiver.v

@@ -24,7 +24,7 @@ module Uart8Receiver (
     output reg busy,     // transaction is in progress
     output reg done,     // end of transaction
     output reg err,      // error while receiving data
-    output reg [7:0] out // received data put back in parallel form
+    output reg [7:0] out // the received data assembled in parallel form
 );
 
 reg [2:0] state          = `RESET;
@@ -85,11 +85,19 @@ always @(posedge clk) begin
     end
 end
 
+/*
+ * Disable at any time in the flow
+ */
 always @(posedge clk) begin
     if (!en) begin
         state <= `RESET;
     end
+end
 
+/*
+ * State machine
+ */
+always @(posedge clk) begin
     case (state)
         `RESET: begin
             // state variables
@@ -100,7 +108,7 @@ always @(posedge clk) begin
             busy           <= 1'b0;
             done           <= 1'b0;
             err            <= 1'b0;
-            out            <= 8'b0; // parallel data output only during {done}
+            out            <= 8'b0; // output parallel data only during {done}
             // next state
             if (en) begin
                 state      <= `IDLE;
@@ -131,7 +139,7 @@ always @(posedge clk) begin
                     end
                 end else begin
                     sample_count      <= sample_count + 4'b1;
-                    if (sample_count == 4'b1011) begin // reached 11
+                    if (sample_count == 4'b1100) begin // reached 12
                         // start signal meets an additional hold time
                         // of >= 4 rx ticks after its own mid-point -
                         // start new full interval count but from the mid-point
@@ -142,7 +150,7 @@ always @(posedge clk) begin
                     end
                 end
             end else if (|sample_count) begin
-                // bit did not remain low while waiting till 7 then 11 -
+                // bit did not remain low while waiting till 8 then 12 -
                 // remain in IDLE state
                 sample_count          <= 4'b0;
                 received_data         <= 8'b0;
@@ -247,7 +255,7 @@ always @(posedge clk) begin
             if (!err && !in_sample) begin
                 // accept the trigger to start, right from stop signal high
                 // (in this case transmit signaling of {done} is in progress)
-                sample_count   <= 4'b0;
+                sample_count   <= 4'b1;
                 out_hold_count <= sample_count + 5'b00010; // continue counting
                 state          <= `IDLE;
             end else if (&sample_count[3:1]) begin // reached 14 -

Uart8Transmitter.v

@@ -14,7 +14,7 @@
  *   (*change before {done} rising edge)
  *
  * Finer control over when to start the next frame is provided by cycling
- *   the {start} input low then driving it high
+ *   the {start} input low then high
  *
  * System clock must be divided down to the baud rate, which is the
  *   {clk} input
@@ -46,26 +46,34 @@ module Uart8Transmitter #(
     input wire [7:0] in, // parallel data to transmit
     output reg busy,     // transmit is in progress
     output reg done,     // end of transmission
-    output reg out       // tx line
+    output reg out       // tx line for serial data
 );
 
 reg [2:0] state     = `RESET;
 reg [7:0] in_data   = 8'b0; // shift reg for the data to transmit serially
 reg [2:0] bit_index = 3'b0; // index for 8-bit data
 
+/*
+ * Disable at any time in the flow
+ */
 always @(posedge clk) begin
     if (!en) begin
         state <= `RESET;
     end
+end
 
+/*
+ * State machine
+ */
+always @(posedge clk) begin
     case (state)
         `RESET: begin
             // state variables
             bit_index <= 3'b0;
             // outputs
             busy      <= 1'b0;
             done      <= 1'b0;
-            out       <= 1'b1; // line is high for IDLE state
+            out       <= 1'b1; // drive the line high for IDLE state
             // next state
             if (en) begin
                 state <= `IDLE;

tests/1.gtkw

@@ -3,12 +3,12 @@
 [*] Sun Oct 16 19:14:34 2022
 [*]
 [dumpfile] "1.vcd"
-[dumpfile_mtime] "Sun Oct 16 19:12:30 2022"
-[dumpfile_size] 1790532
+[dumpfile_mtime] "Fri Dec 23 16:04:41 2022"
+[dumpfile_size] 1792051
 [savefile] "1.gtkw"
 [timestart] 0
 [size] 1536 937
-[pos] -1 -1
+[pos] -9 -9
 *-18.545267 1555000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] test.
 [treeopen] test.uart1.

tests/10.gtkw

@@ -3,12 +3,12 @@
 [*] Sun Oct 23 01:14:48 2022
 [*]
 [dumpfile] "10.vcd"
-[dumpfile_mtime] "Sun Oct 23 01:13:28 2022"
-[dumpfile_size] 2768265
+[dumpfile_mtime] "Fri Dec 23 18:29:48 2022"
+[dumpfile_size] 2770260
 [savefile] "10.gtkw"
 [timestart] 0
 [size] 1536 937
-[pos] -1 -1
+[pos] -9 -9
 *-19.167105 1312000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] test.
 [treeopen] test.uart1.

tests/11.gtkw

@@ -3,8 +3,8 @@
 [*] Sun Oct 23 01:14:48 2022
 [*]
 [dumpfile] "11.vcd"
-[dumpfile_mtime] "Sun Oct 23 01:13:28 2022"
-[dumpfile_size] 2768770
+[dumpfile_mtime] "Fri Dec 23 18:29:59 2022"
+[dumpfile_size] 2771150
 [savefile] "11.gtkw"
 [timestart] 0
 [size] 1536 937

tests/11.v

@@ -85,7 +85,7 @@ always #SIM_TIMESTEP_FACTOR clk = ~clk;
 initial c = 1;
 
 always @(posedge uart1.txClk) begin
-  // drive the start signal low synchronously from the last done signal
+  // drive the start signal low synchronously from the last tx done signal
   if (txDone_1) begin
     c <= c + 1;
     if (c == 2) begin

tests/12.gtkw

@@ -3,13 +3,13 @@
 [*] Sun Oct 23 04:05:20 2022
 [*]
 [dumpfile] "12.vcd"
-[dumpfile_mtime] "Sun Oct 23 03:49:29 2022"
-[dumpfile_size] 2770174
+[dumpfile_mtime] "Fri Dec 23 19:47:31 2022"
+[dumpfile_size] 2770294
 [savefile] "12.gtkw"
 [timestart] 0
 [size] 1536 937
 [pos] -9 -9
-*-19.167105 1274000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-19.167105 1357100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] test.
 [treeopen] test.uart1.
 [treeopen] test.uart2.

tests/13.gtkw

@@ -3,8 +3,8 @@
 [*] Sun Oct 23 04:05:20 2022
 [*]
 [dumpfile] "13.vcd"
-[dumpfile_mtime] "Sun Oct 23 03:49:29 2022"
-[dumpfile_size] 21304401
+[dumpfile_mtime] "Fri Dec 23 19:50:37 2022"
+[dumpfile_size] 21315319
 [savefile] "13.gtkw"
 [timestart] 0
 [size] 1536 937

tests/14.gtkw

@@ -3,8 +3,8 @@
 [*] Sun Oct 23 04:05:20 2022
 [*]
 [dumpfile] "14.vcd"
-[dumpfile_mtime] "Sun Oct 23 03:49:29 2022"
-[dumpfile_size] 19949918
+[dumpfile_mtime] "Fri Dec 23 19:50:49 2022"
+[dumpfile_size] 19960343
 [savefile] "14.gtkw"
 [timestart] 0
 [size] 1536 937

tests/15.gtkw

@@ -3,8 +3,8 @@
 [*] Sun Oct 23 04:55:42 2022
 [*]
 [dumpfile] "15.vcd"
-[dumpfile_mtime] "Sun Oct 23 04:52:51 2022"
-[dumpfile_size] 21305766
+[dumpfile_mtime] "Fri Dec 23 19:51:03 2022"
+[dumpfile_size] 21316839
 [savefile] "15.gtkw"
 [timestart] 0
 [size] 1536 937