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TimRudyTimRudy
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Add stronger condition to recognize start
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6 files changed

+347
-3
lines changed

6 files changed

+347
-3
lines changed

‎Uart8Receiver.v‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -131,15 +131,18 @@ always @(posedge clk) begin
131131
end
132132
end else begin
133133
sample_count <= sample_count + 4'b1;
134-
if (&sample_count[2:0]) begin // reached 7
135-
sample_count <= 4'b0; // start the interval count over
134+
if (sample_count == 4'b1011) begin // reached 11
135+
// start signal meets an additional hold time
136+
// of >= 4 rx ticks after its own mid-point -
137+
// start new full interval count but from the mid-point
138+
sample_count <= 4'b0100;
136139
busy <= 1'b1;
137140
err <= 1'b0;
138141
state <= `START_BIT;
139142
end
140143
end
141144
end else if (|sample_count) begin
142-
// bit did not remain low while waiting till 7 -
145+
// bit did not remain low while waiting till 7 then 11 -
143146
// remain in IDLE state
144147
sample_count <= 4'b0;
145148
received_data <= 8'b0;

‎tests/29.gtkw‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
3+
[*] Thu Dec 22 19:57:56 2022
4+
[*]
5+
[dumpfile] "29.vcd"
6+
[dumpfile_mtime] "Thu Dec 22 19:56:01 2022"
7+
[dumpfile_size] 900848
8+
[savefile] "29.gtkw"
9+
[timestart] 941400
10+
[size] 1536 937
11+
[pos] -9 -9
12+
*-16.818604 1128800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] test.
14+
[treeopen] test.uart.
15+
[sst_width] 197
16+
[signals_width] 290
17+
[sst_expanded] 1
18+
[sst_vpaned_height] 444
19+
@28
20+
test.txByte_1[7:0]
21+
test.rx
22+
test.uart.rxInst.clk
23+
test.uart.rxInst.en
24+
test.uart.rxInst.busy
25+
test.uart.rxInst.done
26+
test.uart.rxInst.err
27+
test.uart.rxInst.in_sample
28+
@c00022
29+
test.uart.rxInst.in_prior_hold_reg[3:0]
30+
@28
31+
(0)test.uart.rxInst.in_prior_hold_reg[3:0]
32+
(1)test.uart.rxInst.in_prior_hold_reg[3:0]
33+
(2)test.uart.rxInst.in_prior_hold_reg[3:0]
34+
(3)test.uart.rxInst.in_prior_hold_reg[3:0]
35+
@1401200
36+
-group_end
37+
@c00022
38+
test.uart.rxInst.in_current_hold_reg[3:0]
39+
@28
40+
(0)test.uart.rxInst.in_current_hold_reg[3:0]
41+
(1)test.uart.rxInst.in_current_hold_reg[3:0]
42+
(2)test.uart.rxInst.in_current_hold_reg[3:0]
43+
(3)test.uart.rxInst.in_current_hold_reg[3:0]
44+
@1401200
45+
-group_end
46+
@22
47+
test.uart.rxInst.sample_count[3:0]
48+
test.uart.rxInst.out_hold_count[4:0]
49+
@28
50+
test.uart.rxInst.state[2:0]
51+
test.uart.rxInst.bit_index[2:0]
52+
test.uart.rxInst.received_data[7:0]
53+
test.uart.rxInst.out[7:0]
54+
[pattern_trace] 1
55+
[pattern_trace] 0

‎tests/29.v‎

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
`timescale 100ns/1ns
2+
`default_nettype none
3+
4+
`include "Uart8.v"
5+
6+
module test;
7+
8+
localparam CLOCK_FREQ = 12000000; // Alhambra board
9+
localparam SIM_STEP_FREQ = 1 / 0.0000001 / 2; // this sim timescale 100ns
10+
11+
// for the simulation timeline:
12+
// ratio SIM_STEP_FREQ MHz / CLOCK_FREQ MHz gives the output waveform in proper time
13+
// (*but note all clocks and the timeline are approximate due to rounding)
14+
localparam SIM_TIMESTEP_FACTOR = SIM_STEP_FREQ / CLOCK_FREQ;
15+
16+
reg clk;
17+
reg en_1;
18+
reg rx;
19+
wire rxBusy_2;
20+
wire rxDone_2;
21+
wire rxErr_2;
22+
reg [7:0] txByte_1;
23+
wire [7:0] rxByte_2;
24+
25+
Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart(
26+
.clk(clk),
27+
28+
// rx interface
29+
.rxEn(en_1),
30+
.rx(rx),
31+
.rxBusy(rxBusy_2),
32+
.rxDone(rxDone_2),
33+
.rxErr(rxErr_2),
34+
.out(rxByte_2)
35+
36+
// tx interface (unused)
37+
);
38+
39+
initial clk = 1'b0;
40+
41+
always #SIM_TIMESTEP_FACTOR clk = ~clk;
42+
43+
initial begin
44+
$dumpfile(`DUMP_FILE_NAME);
45+
$dumpvars(0, test);
46+
47+
// #65 == 1 rx clock period (approximately) at 9600 baud
48+
#240
49+
en_1 = 1'b1;
50+
txByte_1 = 8'b11010110;
51+
rx = 1'b0;
52+
53+
$display(" tx data: %8b", txByte_1);
54+
#160
55+
rx = 1'b1;
56+
#360
57+
rx = 1'b0;
58+
#1075 // instead of #1042, this makes transmit clock sync with receive clock (a 3% difference)
59+
rx = txByte_1[0];
60+
61+
$display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
62+
#1075
63+
rx = txByte_1[1];
64+
65+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
66+
#1075
67+
rx = txByte_1[2];
68+
69+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
70+
#1075
71+
rx = txByte_1[3];
72+
73+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
74+
#1075
75+
rx = txByte_1[4];
76+
77+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
78+
#1075
79+
rx = txByte_1[5];
80+
81+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
82+
#1075
83+
rx = txByte_1[6];
84+
85+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
86+
#1075
87+
rx = txByte_1[7];
88+
89+
$display("%7.2fms | rx last bit: %1b", $realtime/10000, rx);
90+
#530
91+
rx = 1'b1;
92+
#630
93+
rx = 1'b0;
94+
95+
$display("%7.4fms | end of stop bit | start of start bit: %1b", $realtime/10000, rx);
96+
#830
97+
rx = 1'b1;
98+
99+
$display("%7.4fms | end of start bit: %1b", $realtime/10000, rx);
100+
#700
101+
rx = txByte_1[0];
102+
103+
$display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
104+
#1075
105+
rx = txByte_1[1];
106+
107+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
108+
#1075
109+
rx = txByte_1[2];
110+
#1000
111+
112+
$finish();
113+
end
114+
115+
endmodule

‎tests/29a.gtkw‎

Lines changed: 55 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,55 @@
1+
[*]
2+
[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
3+
[*] Thu Dec 22 20:04:47 2022
4+
[*]
5+
[dumpfile] "29a.vcd"
6+
[dumpfile_mtime] "Thu Dec 22 19:56:01 2022"
7+
[dumpfile_size] 900838
8+
[savefile] "29a.gtkw"
9+
[timestart] 941400
10+
[size] 1536 937
11+
[pos] -9 -9
12+
*-16.818604 1128800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
13+
[treeopen] test.
14+
[treeopen] test.uart.
15+
[sst_width] 197
16+
[signals_width] 290
17+
[sst_expanded] 1
18+
[sst_vpaned_height] 444
19+
@28
20+
test.txByte_1[7:0]
21+
test.rx
22+
test.uart.rxInst.clk
23+
test.uart.rxInst.en
24+
test.uart.rxInst.busy
25+
test.uart.rxInst.done
26+
test.uart.rxInst.err
27+
test.uart.rxInst.in_sample
28+
@c00022
29+
test.uart.rxInst.in_prior_hold_reg[3:0]
30+
@28
31+
(0)test.uart.rxInst.in_prior_hold_reg[3:0]
32+
(1)test.uart.rxInst.in_prior_hold_reg[3:0]
33+
(2)test.uart.rxInst.in_prior_hold_reg[3:0]
34+
(3)test.uart.rxInst.in_prior_hold_reg[3:0]
35+
@1401200
36+
-group_end
37+
@c00022
38+
test.uart.rxInst.in_current_hold_reg[3:0]
39+
@28
40+
(0)test.uart.rxInst.in_current_hold_reg[3:0]
41+
(1)test.uart.rxInst.in_current_hold_reg[3:0]
42+
(2)test.uart.rxInst.in_current_hold_reg[3:0]
43+
(3)test.uart.rxInst.in_current_hold_reg[3:0]
44+
@1401200
45+
-group_end
46+
@22
47+
test.uart.rxInst.sample_count[3:0]
48+
test.uart.rxInst.out_hold_count[4:0]
49+
@28
50+
test.uart.rxInst.state[2:0]
51+
test.uart.rxInst.bit_index[2:0]
52+
test.uart.rxInst.received_data[7:0]
53+
test.uart.rxInst.out[7:0]
54+
[pattern_trace] 1
55+
[pattern_trace] 0

‎tests/29a.v‎

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,115 @@
1+
`timescale 100ns/1ns
2+
`default_nettype none
3+
4+
`include "Uart8.v"
5+
6+
module test;
7+
8+
localparam CLOCK_FREQ = 12000000; // Alhambra board
9+
localparam SIM_STEP_FREQ = 1 / 0.0000001 / 2; // this sim timescale 100ns
10+
11+
// for the simulation timeline:
12+
// ratio SIM_STEP_FREQ MHz / CLOCK_FREQ MHz gives the output waveform in proper time
13+
// (*but note all clocks and the timeline are approximate due to rounding)
14+
localparam SIM_TIMESTEP_FACTOR = SIM_STEP_FREQ / CLOCK_FREQ;
15+
16+
reg clk;
17+
reg en_1;
18+
reg rx;
19+
wire rxBusy_2;
20+
wire rxDone_2;
21+
wire rxErr_2;
22+
reg [7:0] txByte_1;
23+
wire [7:0] rxByte_2;
24+
25+
Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart(
26+
.clk(clk),
27+
28+
// rx interface
29+
.rxEn(en_1),
30+
.rx(rx),
31+
.rxBusy(rxBusy_2),
32+
.rxDone(rxDone_2),
33+
.rxErr(rxErr_2),
34+
.out(rxByte_2)
35+
36+
// tx interface (unused)
37+
);
38+
39+
initial clk = 1'b0;
40+
41+
always #SIM_TIMESTEP_FACTOR clk = ~clk;
42+
43+
initial begin
44+
$dumpfile(`DUMP_FILE_NAME);
45+
$dumpvars(0, test);
46+
47+
// #65 == 1 rx clock period (approximately) at 9600 baud
48+
#240
49+
en_1 = 1'b1;
50+
txByte_1 = 8'b11010110;
51+
rx = 1'b0;
52+
53+
$display(" tx data: %8b", txByte_1);
54+
#160
55+
rx = 1'b1;
56+
#360
57+
rx = 1'b0;
58+
#1075 // instead of #1042, this makes transmit clock sync with receive clock (a 3% difference)
59+
rx = txByte_1[0];
60+
61+
$display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
62+
#1075
63+
rx = txByte_1[1];
64+
65+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
66+
#1075
67+
rx = txByte_1[2];
68+
69+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
70+
#1075
71+
rx = txByte_1[3];
72+
73+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
74+
#1075
75+
rx = txByte_1[4];
76+
77+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
78+
#1075
79+
rx = txByte_1[5];
80+
81+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
82+
#1075
83+
rx = txByte_1[6];
84+
85+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
86+
#1075
87+
rx = txByte_1[7];
88+
89+
$display("%7.2fms | rx last bit: %1b", $realtime/10000, rx);
90+
#530
91+
rx = 1'b1;
92+
#630
93+
rx = 1'b0;
94+
95+
$display("%7.4fms | end of stop bit | start of start bit: %1b", $realtime/10000, rx);
96+
#610
97+
rx = 1'b1;
98+
99+
$display("%7.4fms | end of start bit: %1b", $realtime/10000, rx);
100+
#920
101+
rx = txByte_1[0];
102+
103+
$display("%7.2fms | rx first bit: %1b", $realtime/10000, rx);
104+
#1075
105+
rx = txByte_1[1];
106+
107+
$display("%7.2fms | rx next bit: %1b", $realtime/10000, rx);
108+
#1075
109+
rx = txByte_1[2];
110+
#1000
111+
112+
$finish();
113+
end
114+
115+
endmodule

‎tests/Key.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,3 +26,4 @@
2626
26. Error at beginning of next xaction due to rx start signal not meeting its requirement: success accepting previous xaction (*shows done sustained for 16-tick cycle, shows err and reset err)
2727
27. One frame, and next xaction starts during the READY state: success
2828
28: One frame, next xaction does not start in READY state, goes to RESET state: fail to start second xaction because rx stop signal too long (*shows err)
29+
29. Error at beginning of next xaction due to rx start signal not long enough to meet its extra hold requirement: success accepting previous xaction (*shows err)

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