FIR Filter implementation in FPGA

Management and Analysis of Physics Dataset MOD A project

Saverio Monaco

Javier Gerardo Carmona

How to run the filter

1. Create the Xilinx environment

source  /tools/Xilinx/Vivado/2018.3/settings64.sh

2. build your bitstream

make clean; make

3. Program FPGA

make program_fpga

4. In script.py change the USB port according to the correct one (use ls -l /dev/ttyUSB* to find it out)
5. Running the script script.py, the signal present in signal.txt will be sent to the FPGA and filtered
6. After compilation, the filtered signal will be in fromfpga.txt
   
   

A brief explanation of how the filter was made can be found in the report.