[docs][libcpu][arm][cortex-a] add comment for mmu.h

[laidene]

拉取/合并请求描述：(PR description)

[

为什么提交这份PR (why to submit this PR)

添加和修改对mmu.h的宏定义的注释，我认为可以辅助理解代码。

你的解决方案是什么 (what is your solution)

1 添加对 MMU translation table entry format 的字段描述注释。
2 修改部分与文档不符的注释。
3 对齐部分注释和代码。

请提供验证的bsp和config (provide the config and bsp)

• BSP:none
• .config:none
• action:none

]

当前拉取/合并请求的状态 Intent for your PR

必须选择一项 Choose one (Mandatory):

• 本拉取/合并请求是一个草稿版本 This PR is for a code-review and is intended to get feedback
• 本拉取/合并请求是一个成熟版本 This PR is mature, and ready to be integrated into the repo

代码质量 Code Quality：

我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:

• 已经仔细查看过代码改动的对比 Already check the difference between PR and old code
• 代码风格正确，包括缩进空格，命名及其他风格 Style guide is adhered to, including spacing, naming and other styles
• 没有垃圾代码，代码尽量精简，不包含#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up
• 所有变更均有原因及合理的，并且不会影响到其他软件组件代码或BSP All modifications are justified and not affect other components or BSP
• 对难懂代码均提供对应的注释 I've commented appropriately where code is tricky
• 代码是高质量的 Code in this PR is of high quality
• 已经使用formatting 等源码格式化工具确保格式符合RT-Thread代码规范 This PR complies with RT-Thread code specification
• 如果是新增bsp, 已经添加ci检查到.github/ALL_BSP_COMPILE.json 详细请参考链接BSP自查

改动说明

添加对 MMU table entry 的字段解释注释

对照 ARM Cortex-A Series (Armv7-A) Programmer’s Guide(Version 4.0) 添加注释

/**
 * Level 1 translation table entry format
 * 
 * It has 4 types:
 *      Fault type:             bit[1:0] = 0b00
 *      Point L2 page type:     bit[1:0] = 0b01
 *      Section type:           bit[1:0] = 0b10 and bit[18] = 0
 *      Supersection type:      bit[1:0] = 0b10 and bit[18] = 1
 * 
 * The following defines are for section type entry
 *      bit[01:00]: 0b10
 *      bit[02]   : B
 *      bit[03]   : C
 *      bit[04]   : XN
 *      bit[08:05]: Domain
 *      bit[09]   : P
 *      bit[11:10]: AP
 *      bit[14:12]: TEX
 *      bit[15]   : APX
 *      bit[16]   : S
 *      bit[17]   : nG
 *      bit[18]   : 0
 *      bit[19]   : SBZ
 *      bit[31:20]: Section Bass Address
 */

/**
 * Level 2 translation table entry format
 * 
 * it has 3 types:
 *      Fault:       bit[1:0] = 0b00
 *      Larger page: bit[1:0] = 0b01
 *      Small  page: bit[1:0] = 0b1x
 * 
 * The following defines are for small page type entry
 *      bit[00]:    XN
 *      bit[01]:    1
 *      bit[02]:    B
 *      bit[03]:    C
 *      bit[05:04]: AP
 *      bit[08:06]: TEX
 *      bit[09]:    APX
 *      bit[10]:    S
 *      bit[11]:    nG
 *      bit[31:12]: Small Page Base Address
 */

// 其他注释 
/* DACR, Domain n access permission */
#define DOMAIN_FAULT   (0x0)                    /* 0b00: No access */
#define DOMAIN_CHK     (0x1)                    /* 0b01: Client */
#define DOMAIN_NOTCHK  (0x3)                    /* 0b11: No check */


/* DACR */
#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)          /* domain0 use client mode */
#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)        /* domain1 use no access mode */

修改注释

一处与文档描述不符

// 修改前

#ifdef RT_USING_SMART
#define AP_RW          (1<<10) /* supervisor=RW, user=No */
#define AP_RO          ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ /* 此处与文档不符 */
#else
#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
#define AP_RO          (2<<10) /* supervisor=RW, user=RO */
#endif

// 修改后

/* memory access permissions(AP APX) */
#ifdef RT_USING_SMART
#define AP_RW           (1<<10)                 /* supervisor=RW, user=No */
#define AP_RO           ((1<<10) | (1 << 15))   /* supervisor=RO, user=No */
#else
#define AP_RW           (3<<10)                 /* supervisor=RW, user=RW */
#define AP_RO           (2<<10)                 /* supervisor=RW, user=RO */
#endif

删除部分注释

// 修改前
#define SHARED         (1<<16) /* shareable */ /* 因为我在最上面描述个整个 entry format 所以删除 */
#define XN             (1<<4)  /* eXecute Never */

/* device mapping type */
#define DEVICE_MEM     (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
/* normal memory mapping type */
#define NORMAL_MEM     (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)

#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)


// 修改后

#define SHARED          (1 << 16)
#define XN              (1<<4)


/* Memory types */
#define DEVICE_MEM       (SHARED|AP_RW|DOMAIN0|SHAREDEVICE|DESC_SEC|XN)
#define NORMAL_MEM       (SHARED|AP_RW|DOMAIN0|MEMWBWA|DESC_SEC)
#define STRONG_ORDER_MEM (SHARED|AP_RO|XN|DESC_SEC)

对齐代码

#define RT_HW_MMU_PROT_READ 1
#define RT_HW_MMU_PROT_WRITE 2
#define RT_HW_MMU_PROT_EXECUTE 4
#define RT_HW_MMU_PROT_KERNEL 8
#define RT_HW_MMU_PROT_USER 16
#define RT_HW_MMU_PROT_CACHE 32

// 修改后
#define RT_HW_MMU_PROT_READ    1
#define RT_HW_MMU_PROT_WRITE   2
#define RT_HW_MMU_PROT_EXECUTE 4
#define RT_HW_MMU_PROT_KERNEL  8
#define RT_HW_MMU_PROT_USER    16
#define RT_HW_MMU_PROT_CACHE   32

测试

纯格式和注释修改，不影响功能

[github-actions]

👋 感谢您对 RT-Thread 的贡献！Thank you for your contribution to RT-Thread!

为确保代码符合 RT-Thread 的编码规范，请在你的仓库中执行以下步骤运行代码格式化工作流（如果格式化CI运行失败）。
To ensure your code complies with RT-Thread's coding style, please run the code formatting workflow by following the steps below (If the formatting of CI fails to run).

---

🛠 操作步骤 | Steps

1. 前往 Actions 页面 | Go to the Actions page
   点击进入工作流 → | Click to open workflow →

2. 点击 Run workflow | Click Run workflow

• 设置需排除的文件/目录（目录请以"/"结尾）
  Set files/directories to exclude (directories should end with "/")
• 将目标分支设置为 \ Set the target branch to：docs/libcpu/arm/cortex-a
• 设置PR number为 \ Set the PR number to：11104

3. 等待工作流完成 | Wait for the workflow to complete
   格式化后的代码将自动推送至你的分支。
   The formatted code will be automatically pushed to your branch.

完成后，提交将自动更新至 docs/libcpu/arm/cortex-a 分支，关联的 Pull Request 也会同步更新。
Once completed, commits will be pushed to the docs/libcpu/arm/cortex-a branch automatically, and the related Pull Request will be updated.

如有问题欢迎联系我们，再次感谢您的贡献！💐
If you have any questions, feel free to reach out. Thanks again for your contribution!

[CLAassistant]

All committers have signed the CLA.