aarch64: document the CNTFRQ_EL0

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[Copilot]

Pull Request Overview

This PR adds documentation comments to clarify the behavior of the CNTFRQ_EL0 register in the AArch64 architecture. The change explains that only the lower 32 bits of the counter-timer frequency register are effective, as bits [63:32] are reserved according to the ARM architecture specification.

Key Changes:

• Added documentation comment explaining CNTFRQ_EL0 register bit allocation
• Clarified that only bits [31:0] contain valid frequency data