Hi, I'm Narsimha Raj
RTL Design & Verification Engineer building industry-oriented digital blocks — from RTL and FPGA integration through functional verification, wave-based debug, and verification automation.
I develop synchronous and asynchronous FIFOs, AXI-Stream interfaces, processor datapaths, and CDC-oriented designs, with hands-on flows in SystemVerilog/Verilog, ModelSim, GTKWave, and Vivado. My GitHub is my portfolio: block-level RTL, testbench bring-up, and Python-based DV scripting aligned with how silicon teams work.
- 🔧 RTL & digital architecture — FSM-centric design, bus/FIFO blocks, and structured RTL for simulation and FPGA flows
- 🧪 Functional verification — SystemVerilog testbenches, stimulus/checkers, linting, and waveform-driven debug
- ⚙️ Verification automation — Python scripting to streamline regression-style checks and DV workflows
- 📐 FPGA-oriented integration — RTL-to-bitstream mindset with Vivado and Linux-based tool environments
- 🛠️ Engineering discipline — Git-tracked projects, reproducible sim setups, and industry-style repo organization
| Project | Focus | Link |
|---|---|---|
| Verification Automation | Python DV — logs, regression, coverage | verification-automation |
| Async FIFO | Dual-clock · Gray pointers · CDC | FIFO_ASYNC |
| Sync FIFO Study | 3 full/empty architectures compared | FIFO_S |
| AXI-Stream FIFO | SystemVerilog stream buffering | AXIS_FIF0 |
| AXI-Stream M/S | Handshake · packet transfer | AXI_STREAM |
| MIPS Single-Cycle | 32-bit CPU datapath + control | MIPS_32_SINGLE_CYCLE |
| CDC Techniques | Synchronizers · handshake · reference | CDC_TECHNIQUES |
| Area | Direction |
|---|---|
| RTL Design | Parameterized digital blocks — FIFOs, stream interfaces, and datapath logic with clean, reviewable RTL |
| FPGA Architectures | Synthesis-aware RTL and Vivado-oriented integration for deployable prototypes |
| Verification Automation | Python-based tooling to accelerate regressions, checks, and repeatable DV workflows |
| SystemVerilog Verification | Structured testbenches, debug with ModelSim/GTKWave, and lint-driven quality |
| Python-based DV Scripting | Flow automation around simulation, reporting, and project maintainability |
Open to RTL Design, FPGA, and Design Verification opportunities where structured RTL, solid verification, and automation matter.
If you're hiring, reviewing portfolios, or collaborating on VLSI block-level work — reach out on LinkedIn or explore my repos on GitHub.
Designing reliable digital hardware — verified, debugged, and automation-ready.
