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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

feat(constantin): add custom constantin file module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: utility RTL utility note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5836 opened Apr 20, 2026 by Maxpicca-Li Member Loading…
3 tasks
1
timing(ftq): add some additional pipelines in FTQ module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#5835 opened Apr 20, 2026 by Yan-Muzi Contributor • Draft
1
feat(VirtualStoreQueue): add support of pre-allocated storeQueue module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5834 opened Apr 20, 2026 by weidingliu Member • Draft
fix(csr): fix indirect csr RegOut module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5833 opened Apr 20, 2026 by sinceforYy Contributor Loading…
1
test 20260417 release module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5828 opened Apr 17, 2026 by good-circle Contributor • Draft
fix(LoadUnit): prefetch does not trigger an exception module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5827 opened Apr 17, 2026 by Anzooooo Member • Draft
submodule(difftest): bump difftest for kmh-v3 module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5826 opened Apr 17, 2026 by klin02 Member Loading…
1
submodule(difftest): bump difftest for kmh-v2 module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5825 opened Apr 17, 2026 by klin02 Member Loading…
fix(csr): fix indirect csr RegOut module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#5823 opened Apr 17, 2026 by sinceforYy Contributor Loading…
ci(emu): disable lightSSS for gsim jobs module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc.
#5822 opened Apr 16, 2026 by ngc7331 Member Loading…
3
refactor(frontend): drop unused wrbypass module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: code quality To make code more readable & maintainable
#5821 opened Apr 16, 2026 by ngc7331 Member Loading…
1
area(sc): SC train data changed from meta to re-read module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: area To reduce area comsuption
#5819 opened Apr 16, 2026 by sleep-zzz Contributor Loading…
1
feat(CtrlUnit): add two regs for limiting addr range module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5817 opened Apr 15, 2026 by Ruomio • Draft
Test for sbuffer size 16 -> 32 (and sbuffer threshold = 12) module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5816 opened Apr 15, 2026 by jlong299 Contributor Loading…
1
feat(dispatch): add switch to disable dispatch balance opt module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs
#5815 opened Apr 15, 2026 by xiaofeibao-xjtu Contributor Loading…
1
feat(missQueue, sbuffer): sbuffer releases the entry when miss accepted by mshr, and mshr provides st-ld forwarding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5813 opened Apr 14, 2026 by jlong299 Contributor Loading…
7
tmp module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: other ChiselAIA, IMSIC, CLINT, etc. module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: utility RTL utility note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5811 opened Apr 14, 2026 by Tang-Haojin Member • Draft
1
fix(LoadUnit): clear replay cause on matchInvalid writeback module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5810 opened Apr 14, 2026 by maxiaoran24 Loading…
1
area(tage): use SRAM to store usefulCtr module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: area To reduce area comsuption
#5805 opened Apr 13, 2026 by TheKiteRunner24 Collaborator • Draft
1
refactor(StoreBuffer, difftest): Update Store difftest logic and clea… module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5802 opened Apr 13, 2026 by skyhgzsh Contributor • Draft
6
run CI - perf(sbuffer): change StoreBufferThreshold 7 -> 12 module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5800 opened Apr 10, 2026 by jlong299 Contributor Loading…
1
fix: issue related lowpower asyncBridge module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5799 opened Apr 10, 2026 by yulightenyu Contributor • Draft
timing(bpu): fix bpu s3 timing module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5797 opened Apr 10, 2026 by TheKiteRunner24 Collaborator Loading…
3
feat(VirtualLoadQueue): add pointer exceed assert for debug module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5795 opened Apr 10, 2026 by weidingliu Member Loading…
1
fix(backend, ctrlblock): export empty state to ftq when backend drains module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5787 opened Apr 8, 2026 by wissygh Contributor Loading…
3
ProTip! Updated in the last three days: updated:>2026-04-17.