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build-uefi.sh: Clarify the usage instructions #9

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@Baitinq Baitinq commented Dec 22, 2022

This patch adds a bit of clarification on how this script should be used and the needed prerequisites for the script to successfully build coreboot.

P.S. I think this would be useful (at least for me) as it would've saved me quite a lot of time of me banging my head against the wall :))

@Baitinq
build-uefi.sh: Clarify the usage instructions
7c39fd6 
This patch adds a bit of clarification on how this script should be used
and the needed prerequisites for the script to successfully build
coreboot.
@MrChromebox
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MrChromebox commented Dec 22, 2022

so, the blobs needed to build any board for which I have a config are already in the 3rdparty/blobs folder, and checking out the blobs submodule is part of the coreboot setup process as documented on doc.coreboot.org

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Baitinq commented Dec 23, 2022 •
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I did execute git submodule update --init --checkout but I still needed to include the binary blobs for my thinkpad x230 (maybe they are not present in the included blobs? or I may be very possibly doing something wrong :))

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MrChromebox commented Dec 23, 2022

that's correct, since there are lots of variations for the x230's blobs - stock, ME disabled/neutered/shrunk, IFD/BIOS region resized, etc

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Baitinq commented Dec 23, 2022

Makes sense, ty. Should I close this pr then? Or maybe change my wording to represent what you've just said/just add the usage comment?

MrChromebox pushed a commit that referenced this pull request Aug 19, 2023
@kapil-porwal
mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controller
d88039c 
Restrict ASPM to L1 for SD controller to avoid AERs.

BUG=b:288830220
TEST=No PCIE AER on SD controller on Screebo.

w/o this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1-

~ # dmesg | grep -i -e "pci.*error"
[    0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    0.735258] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0
[    1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
[    1.548894] rtsx_pci 0000:02:00.0:   device [10ec:522a] error status/mask=00001000/00006000
[    1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0
```

w/ this CL -
```
~ # lspci -s 00:06.0 -vvv | grep -i aspm
  LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us
          ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # lspci -s 02:00.0 -vvv | grep -i aspm
  LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us
          ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+
  LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+
  L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+
  L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+

~ # dmesg | grep -i -e "pci.*error"

```

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MrChromebox pushed a commit that referenced this pull request Feb 14, 2024
@felixheld
mb/google/nissa: Skip GPP_F15 GPIO locking to avoid IRQ storm
bb41e69 
There is an existing issue for nissa where wake up from RTC wake is not working during suspend_stress_test.

The phenomenon of the issue is that after pulling out the stylus, can see an interrupt storm occurs, checking through:
"cat /proc/interrupts | grep acpi".

When the counter of interrupt is greater than a certain value, "Disabling IRQ #9" will occur, so RTC wake is not working.

Reference: https://review.coreboot.org/c/coreboot/+/65086

This patch skips the locking for GPP_F15 to allow kernel to
configure it later. The interrupt storm of acpi disappears.

BUG=b:321348117
TEST=1. cat /proc/interrupts | grep acpi
there isn't interrupt storm of acpi when pulling out stylus.
2. The stylus tools panel will pop up when pulling out it.
3. Inserts stylus can wakeup DUT after powerd_dbus_suspend.
4. Passed:
   suspend_stress_test -c 2500 --suspend_min=15 --suspend_max=20

Change-Id: Ie143c43e0555d17d8a290f17637b537fba806144
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80316
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@Baitinq @MrChromebox