Skip to content
View MainakSil's full-sized avatar
💭
☕ Fuelled by coffee and code!
💭
☕ Fuelled by coffee and code!
  • VIT-AP University
  • Vijayawada, AP, India

Block or report MainakSil

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
MainakSil/README.md

Hi, I'm Mainak Sil 👋

LinkedIn GitHub Followers

Profile

Electronics and Communication Engineering student with a strong interest in VLSI, communication systems, and embedded systems.
Focused on building practical skills through projects and research, with a goal of solving real-world engineering problems through software-hardware integration.

Education

B.Tech in Electronics and Communication Engineering
VIT-AP University
2023 – 2027 (Currently in 6th semester)

Relevant Coursework

  • Data Structures and Algorithms
  • Object-Oriented Programming (Java)
  • Signals and Systems
  • Control Systems
  • Communication Systems
  • Digital Signal Processing
  • Semiconductor Physics
  • Applied Electromagnetics

Skills

Programming

  • Python, Java, C, C++
  • MATLAB, R
  • Embedded C
  • Assembly (8085, ARM)
  • Verilog, SystemVerilog

Core ECE

  • Semiconductor Devices
  • Microprocessors and Microcontrollers
  • Analog Circuits
  • Control Systems
  • Communication Systems
  • Electromagnetics
  • Digital Signal Processing
  • HDL Verification

Tools

  • Vivado
  • UVM

Currently Learning

  • Cadence Virtuoso
  • CMOS VLSI Design
  • Linear Integrated Circuits
  • Digital System Design (ASICs and FPGAs)
  • Robotics and Automation

Foreign Languages

  • French (Elementary)

@MainakSil's activity is private