This project involves the design and implementation of a Clap Counter Peripheral for an FPGA-based SCOMP processor. The peripheral processes external audio inputs, such as claps or snaps, and provides real-time feedback to the processor. The primary goals of this project were to achieve robust snap detection, ensure accurate counting without overcounting, and provide configurable loudness thresholds. The project was implemented in VHDL and simulated using ModelSim, with a focus on readability, debuggability, and ease of code modification.
- Introduction
- Technologies Used
- Design Overview
- Project Structure
- Setup and Installation
- Key Features
- Simulation Results
- Contributors
- License
This project was developed as part of a course on digital design and FPGA development at Georgia Tech. The Clap Counter Peripheral is designed to interface with the SCOMP processor, processing audio data to detect claps (or snaps) and count them accurately. The design is focused on robustness and configurability, making it adaptable to various environments and use cases.
- VHDL: Hardware description language used to design the clap counter peripheral.
- ModelSim: Simulation tool used to verify the VHDL code.
- Quartus Prime/Xilinx ISE: FPGA development tools for synthesis and implementation.
- SCOMP Processor: A simple computer processor model used as the core CPU for interfacing with the peripheral.
The Clap Counter Peripheral processes audio signals from a microphone and provides two outputs to the SCOMP processor:
- Clap Count: A 15-bit unsigned vector representing the number of claps detected since the last reset.
- Clap Signal: A single bit that toggles whenever a clap is detected.
The peripheral's interface is designed to be straightforward, with the clap count and signaling bit forming the core of the API. Users can configure the loudness threshold through the SCOMP’s IO bus, ensuring that the peripheral only detects claps that exceed a specified loudness.
Users can set the loudness threshold using the 10 LSBs of the SCOMP’s IO bus. The peripheral stops detecting claps when the MSB of the input is set to high. This design allows the peripheral to operate in various environments by adjusting the sensitivity to sound.
The transition from a nested if-statement logic to a state machine was a critical design decision. The state machine improves code readability, debuggability, and maintainability. It operates in three states:
- Start Timer: Initiates the timer when the audio average exceeds the loud threshold.
- Stop Timer: Halts the timer when the audio falls below the quiet threshold.
- Clap Detection: Checks the duration of the noise to confirm if it was a clap and increments the counter.
To filter out small fluctuations in the audio signal, which could lead to false detections, the peripheral uses a moving average of the past 32 samples of the audio data. This approach smooths out the input and improves the accuracy of clap detection.
├── SCOMP.vo # VHDL/Verilog object file for the SCOMP processor
├── SCOMP_modelsim.xrf # ModelSim report file
├── SCOMP.sft # Synthesis report file
├── src/ # Source code directory containing HDL files
│ ├── clap_counter.vhd # VHDL code for the Clap Counter Peripheral
│ ├── clap_counter_tb.vhd # Testbench for the Clap Counter Peripheral
├── simulation/ # Simulation result files and waveforms
│ ├── clap_wave.do # Waveform configuration file for ModelSim
│ ├── clap_wave.wlf # Waveform output file from ModelSim
├── README.md # Project documentation
🛠️ Setup and Installation
Prerequisites
ModelSim: Required for simulating the VHDL code.
Quartus Prime/Xilinx ISE: Required for synthesis and FPGA implementation.
SCOMP Processor: Integrated with the peripheral for testing.
Installation Steps
Clone the repository:
bash
Copy code
git clone https://github.com/yourusername/clap-counter-peripheral.git
cd clap-counter-peripheral
Open the project in ModelSim:
Import the VHDL files from the src/ directory into ModelSim.
Set up the simulation environment using the provided .do files.
Run the simulation:
Simulate the VHDL code to verify the functionality of the Clap Counter Peripheral.
Analyze the waveforms to ensure accurate detection and counting of claps.
Synthesize the design:
Use Quartus Prime or Xilinx ISE to synthesize the design for FPGA implementation.
Generate the bitstream for uploading to an FPGA board.
✨ Key Features
Snap Detection
Robust Clap Detection: The peripheral reliably detects claps without overcounting, using a state machine to manage detection logic.
Configurable Thresholds
User-Defined Sensitivity: The loudness threshold is configurable, allowing the peripheral to adapt to different environments by adjusting the sensitivity to audio input.
State Machine Implementation
Improved Readability and Debuggability: Transitioning to a state machine made the design more maintainable and easier to debug, enhancing the overall reliability of the peripheral.
Moving Averager
Noise Filtering: The moving averager smooths out audio data, reducing the likelihood of false positives and ensuring accurate clap detection.
📊 Simulation Results
Functional Verification: The Clap Counter Peripheral was successfully verified using ModelSim, with accurate detection and counting of claps.
Waveform Analysis: The simulation waveforms confirm the correct operation of the state machine and the timing of the clap detection logic.
Waveform showing the detection and counting of claps by the Clap Counter Peripheral.
👥 Contributors
[Your Name] - FPGA and Digital Design Engineer
Expertise in VHDL, FPGA design, and digital logic simulation.
Developed this project as part of a coursework at Georgia Tech, demonstrating skills in hardware design and simulation.
LinkedIn | GitHub
📝 License
This project is licensed under the MIT License - see the LICENSE file for details.
📝 Clap Counter Peripheral Design Review
Ashan Deen
Submitted April 24th, 2023
Introduction
This document contains information on the peripheral’s functions, their implementation, and the reasoning behind the implementation. The robustness of the snap detection of not overcounting snaps was prioritized along with ease of code formatting, followed by documentation of VHDL code and project as well as assembly coding.
All deliverables of the proposal being a snap counter, snap detection, and configurable thresholds were met except for using a toggle bit instead of a flag bit for snap detection as the external program could never latch on to the flag bit whenever it was high.
Note: Snap and clap are used interchangeably in the document.
Device Functionality
API: The audio peripheral processes external audio from a microphone and provides two pieces of information to SCOMP: a 15-bit unsigned vector containing the number of claps detected since last reset and a clap signaling bit. The peripheral toggles the LSB whenever it detects a clap and increments the clap count by one.
Configurable Thresholds: The user can set a loudness threshold using the ten LSBs of SCOMP’s IO bus. The peripheral stops detecting claps when the MSB of the input is set to high. A special case of our peripheral is when the loud threshold is set below the quiet threshold, which results in rapid incrementation of the counter while sound is below the quiet threshold.
Design Decisions and Implementation
Timer: The timer is in a separate process to make it independent of the state machine. The timer uses an external 10 Hz clock instead of the system clock to put the duration between ticks within an order of magnitude of the duration of a standard clap.
Moving Averager: To filter out small fluctuations in the audio, which could cause false detections, the hardware keeps a running average of the past 32 samples of AUD_DATA using a shift register. This average is used as input to the state machine.
Input Processor: This process formats the input data from SCOMP in a way that can be used as the loud threshold. The peripheral expects a binary number input within the first 10 LSBs, which is