GitHub - LoayMoh99/RISC-5-stages-Processor: A 5 stages pipelined RISC processor for Computer Architecture Course

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
ControlUnit.vhd		ControlUnit.vhd
DataMemory.vhd		DataMemory.vhd
Decoder.vhd		Decoder.vhd
EXtoMEMbuffer.vhd		EXtoMEMbuffer.vhd
FDbuffer.vhd		FDbuffer.vhd
FU.vhd		FU.vhd
FetchUnit.vhd		FetchUnit.vhd
FlushRegister.vhd		FlushRegister.vhd
HazardDetectionUnit.vhd		HazardDetectionUnit.vhd
InstructionMemory.vhd		InstructionMemory.vhd
Mux4x1.vhd		Mux4x1.vhd
N-BitFA.vhd		N-BitFA.vhd
OneBitFA.vhd		OneBitFA.vhd
PC.vhd		PC.vhd
RISC.vhd		RISC.vhd
decExeBuffer.vhd		decExeBuffer.vhd
decodingpart.vhd		decodingpart.vhd
fallingReg.vhd		fallingReg.vhd
finall.cr.mti		finall.cr.mti
finall.mpf		finall.mpf
hALU.vhd		hALU.vhd
hCCR.vhd		hCCR.vhd
hexecute.vhd		hexecute.vhd
memWBbuffer.vhd		memWBbuffer.vhd
memorystage.vhd		memorystage.vhd
mux1.vhd		mux1.vhd
mux1bit4x1.vhd		mux1bit4x1.vhd
mux2.vhd		mux2.vhd
mux4.vhd		mux4.vhd
register.vhd		register.vhd
registerNoClk.vhd		registerNoClk.vhd
regsfile.vhd		regsfile.vhd
spRegister.vhd		spRegister.vhd
stackadder.vhd		stackadder.vhd
zeroextend.vhd		zeroextend.vhd
zeroextend1.vhd		zeroextend1.vhd
zeroextend2.vhd		zeroextend2.vhd
zeroextract.vhd		zeroextract.vhd