UART- Config register -Yuqing Li #45
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Implement UART module with AXI-Lite interface and FIFO support.
the code for config register
kh098760
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Dec 10, 2025
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This is good for a start however:
- if (awvalid && wvalid && awready && wready) works for everything coming in one cycle, but these handshakes might come in different times. It would be better to separate the address and data handshake bits into different if blocks in case if there are stalls.
-ensure no back-to-back writes can occur where the address or data changes during write
-include the response (resp) logic as well
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ok, so you want me to break the code for the address and data to be separate correct. In other words, insert a code to check the address and another to check the if the data is ready to be written that maybe coming into the UART at different time cycle. |
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…On Thu, Dec 11, 2025 at 7:51 PM DevQing66 ***@***.***> wrote:
*DevQing66* left a comment (IEEE-UCF/Gaming-CPU-Project#45)
<#45 (comment)>
This is good for a start however:
- if (awvalid && wvalid && awready && wready) works for everything
coming in one cycle, but these handshakes might come in different times. It
would be better to separate the address and data handshake bits into
different if blocks in case if there are stalls.
-ensure no back-to-back writes can occur where the address or data
changes during write
-include the response (resp) logic as well
ok, so you want me to break the code for the address and data to be
separate correct. In other words, insert a code to check the address and
another to check the if the data is ready to be written that maybe coming
into the UART at different time cycle.
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The code for the config register part on UART is finished. can you check if i am missing anything for this part.