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  1. PW1 PW1 Public

    Archived v1 (2024) of my personal website — Bootstrap single-page. Superseded by PW3.

    CSS

  2. PW2 PW2 Public

    Archived v2 (2024) of my personal website — interactive rebuild. Superseded by PW3.

    JavaScript

  3. Data-Platform-Confluent-Kafka Data-Platform-Confluent-Kafka Public

  4. Historic-Data-Loading Historic-Data-Loading Public

  5. PW3 PW3 Public

    JavaScript

  6. Pipelined-MIPS-CPU Pipelined-MIPS-CPU Public

    5-stage pipelined 32-bit MIPS CPU in Verilog — hazard detection, EX/MEM/decode forwarding, 2-bit BHT/BTB branch prediction, split I/D caches, interactive browser pipeline simulator. CMPEN 331, The …

    Verilog