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Add method to check if bus is dominant #51

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Merged
Ironedde merged 1 commit into from
Feb 4, 2025
Merged

Add method to check if bus is dominant #51

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1 change: 1 addition & 0 deletions mcan/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
Tagging in git follows a pattern: `mcan/<version>`.

## [Unreleased]
- Add method to check if bus is dominant (#51)

## [0.5.0] - 2024-03-04

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7 changes: 7 additions & 0 deletions mcan/src/bus.rs
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Expand Up @@ -199,6 +199,9 @@ pub trait DynAux {
///
/// If timestamping is disabled, its value is zero.
fn timestamp(&self) -> u16;

/// Returns `true` if the CAN bus is dominant.
fn is_dominant(&self) -> bool;
}

impl<Id: mcan_core::CanId, D: mcan_core::Dependencies<Id>> Aux<'_, Id, D> {
Expand Down Expand Up @@ -242,6 +245,10 @@ impl<Id: mcan_core::CanId, D: mcan_core::Dependencies<Id>> DynAux for Aux<'_, Id
fn timestamp(&self) -> u16 {
self.reg.tscv.read().tsc().bits()
}

fn is_dominant(&self) -> bool {
self.reg.test.read().rx().bit_is_clear()
}
}

/// A CAN bus in configuration mode. Before messages can be sent and received,
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